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- User Since
- May 10 2014, 2:21 PM (523 w, 1 d)
Fri, May 17
Looks like I put the wrong review link in rG5270cc9757fb4e0c1303ec44c2602b75acf3806d
Wed, May 15
I have a few fixes for some of the build issues with gcc, but c++ bits of world and kernel modules are broken.
Tue, May 14
Update the comment
Mon, May 13
Untested, but looks correct based on earlier changes from @jhibbits
Fri, May 10
Wed, May 8
Tue, May 7
Rebase on new macros
Fri, May 3
Thu, May 2
I've been thinking about adding PAGE_SIZE_MAX/PAGE_SHIFT_MAX or similar to arm64 to define the largest page size the kernel could support. We could then use that here if it's defined.
Tue, Apr 30
Mon, Apr 29
Wed, Apr 24
I've thought about this and think we should only read ap_cpuid after the MMU is enabled. The same physical address should be mapped with the same memory type for all virtual addresses, however this isn't possible for ap_cpuid when the MMU is disabled.
Tue, Apr 23
A flag. https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst#st_other-values lists it under Processor specific st_other flags.
Apr 19 2024
- Fix a comment
- Remove debugging
Given it's a single instruction being written we could just ignore DIC & IDC, I expect the overhead would be less than a system call & this is an uncommon operation. We wouldn't even need to read ctr_el0 as the smallest cacheline size is the same as the instruction size.