arm64: Add MRS_SAFE to hold a safe ID field value

To support reworking the arm64 CPU ID code to add CTR_EL0, the cache
type register, start to move the safe value to be encoded as a named
field rather than part of MRS_EXACT.

Reviewed by: imp
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D47120