They are a bit more informative than raw hexadecimal values.
While here, sort existing defines of bits for AMD MSRs to match the address
order.
Sponsored by: The FreeBSD Foundation
Differential D41816
x86: Add defines for workaround bits in AMD's MSR "Decode Configuration" olce on Sep 11 2023, 8:21 PM. Authored by Tags None Referenced Files
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They are a bit more informative than raw hexadecimal values. While here, sort existing defines of bits for AMD MSRs to match the address Sponsored by: The FreeBSD Foundation
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