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x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"

Description

x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"

They are a bit more informative than raw hexadecimal values.

While here, sort existing defines of bits for AMD MSRs to match the address
order.

Reviewed by: kib, emaste
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D41816

(cherry picked from commit 125bbadf6084ac341673c9eb1979a740d3d5899a)
(cherry picked from commit d0c0dcf9db7e558a58fbec2d49c293d118ea6979)

Approved by: re (gjb)

Details

Provenance
olceAuthored on Sep 11 2023, 1:10 PM
emasteCommitted on Oct 13 2023, 11:14 PM
Reviewer
kib
Differential Revision
D41816: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"
Parents
rGf28965bcaa1f: udp: fix sending of IPv4-mapped addresses
Branches
Unknown
Tags
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