arm64: make the setting of VM_NFREEORDER and the comment describing it match

[alc]

Summary

The setting of VM_NFREEORDER and the comment describing it were copied from sparc64 where both the page size and the number of page table entries that fit in a cache line are different from arm64.

[kib]

Does TLB miss cause cache miss?

[kib]

In D40782#928081, @kib wrote:

Does TLB miss cause cache miss?

I mean, this is something specific to virtually indexed caches (sparc64) as well.

[andrew]

It might pay to include the assumed cache line size, e.g. most CPUs seem to use a 64 byte cache line, but on some its 128 bytes.

[alc]

In D40782#928081, @kib wrote:

Does TLB miss cause cache miss?

Generally, the MMU's page walker accesses the page table through the cache hierarchy. In fact, on early amd64 machines, a large fraction of the gains from superpages for applications with poor locality of reference came from reducing the size of the page table so that more of the page table entries could be found in the L2 cache on a TLB miss.

[alc]

Address Andrew's comment.

Elaborate on why cache misses occur.