arm64/disassem.c: Add shifted register definitions with ror

[koliagogsadze_gmail.com]

Summary

Add disassembly support for the following shifted register instructions:

• mvn
• orn
• orr
• and
• ands
• bic
• bics
• eon
• eor
• tst

According to Arm64 documenation, operational pseuducode of shifted
register instruction must return UNDEFINED if shift type is RESERVED
('11'). Hence, removed "rsv" from shift_2 array and added "ror".
In case of shift type is 4 and this type is RESERVED,
we will return undefined.

Test Plan

https://github.com/toor1245/freebsd-src/pull/2

[koliagogsadze_gmail.com]

refs:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MVN--Bitwise-NOT--an-alias-of-ORN--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ORN--shifted-register---Bitwise-OR-NOT--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ORR--shifted-register---Bitwise-OR--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/AND--shifted-register---Bitwise-AND--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ANDS--shifted-register---Bitwise-AND--shifted-register---setting-flags-
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/BIC--shifted-register---Bitwise-Bit-Clear--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/BICS--shifted-register---Bitwise-Bit-Clear--shifted-register---setting-flags-
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/EON--shifted-register---Bitwise-Exclusive-OR-NOT--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/EOR--shifted-register---Bitwise-Exclusive-OR--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/TST--shifted-register---Test--shifted-register---an-alias-of-ANDS--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MOV--register---Move--register---an-alias-of-ORR--shifted-register--?lang=en

[mhorne]

sys/arm64/arm64/disassem.c

492

I think it is slightly better named as has_shift_ror.

[mhorne]

LGTM otherwise.

[koliagogsadze_gmail.com]

Changed is_shift_ror to has_shift_ror and fixed check shift type.
For testing RESERVED case (shift == 3) I added instruction manually

.macro ADDS_SHIFT_RSV_64 xd, xn, xm, shift, imm
	.inst	((0b10101011 << 24) | (\shift << 22) | \
		(0b0 << 21) 	    | (\xm << 16)    | \
		(\imm << 10)	    | (\xn << 5)     | \
		(\xd << 0))
.endm

# adds	x0, x1, x3, RESERVED #1
ADDS_SHIFT_RSV_64 0, 1, 3, 3, 1

ref: https://github.com/toor1245/freebsd-src/pull/2/files