arm64/disassem.c: Add shifted register definitions with ror

Add disassembly support for the following shifted register instructions:

• mvn
• orn
• orr
• and
• ands
• bic
• bics
• eon
• eor
• tst

According to Arm64 documenation, operational pseuducode of shifted
register instruction must return UNDEFINED if shift type is RESERVED
('11'). Hence, removed "rsv" from shift_2 array and add "ror". In case
of shift type is 3 and this type is RESERVED, we will return
undefined.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D40386

(cherry picked from commit 9aef25d2686b9e7fb9cb700d63291338e8e30bb6)