Add arm64 CnP support

[andrew]

Summary

Set the Common not Private bit in the ttbr registers when supported on
arm64. This tells the hardware it can share the translation table
entries on multiple CPUs.

[kib]

sys/arm64/arm64/pmap.c

6590

You could replace this boolean with the value to or ttbr with. Then you can avoid one jump in pmap_to_ttbr0().

6619

Unable is the strange term. Do you mean that userspace is not yet activated, so there is no address switching done?

BTW I do not see why do you need to do this from the callback, instead of setting the value before calling IPI.

[andrew]

Switch to using a flag we or in to the ttbr

[andrew]

Reword the comment in pmap_set_cnp

[alc]

I'm quite surprised to see this feature supported by the Graviton 2. I would only have expected to see this feature on micro-architectures that implement SMT/hyperthreading. In fact, the last paragraph of https://developer.arm.com/documentation/101811/0101/Address-spaces-in-AArch64 essentially says so. I wonder if it's simply a NOP on Graviton 2.

sys/arm64/arm64/pmap.c

6641–6642

I would suggest adding a comment explaining why you defer enabling CnP until all of the cores are running.

[andrew]

9e0716f4610158936c0b9cec1a9930c4ebe924fb