pci: Add Synopsys Designware PCIe controller quirk

[pan_semihalf.com]

Summary

The Synopsys Designware PCIe controller causes devices on bus 0 to
appear twice. This is mitigated by manually blocking slots 1 and
higher on bus 0.

[val_packett.cool]

sys/dev/pci/pci_host_generic.h

92

maybe name it PCIE_ECAM_DESIGNWARE_QUIRK? Armada8k is not the only SoC with this quirk…

sys/dev/pci/pci_host_generic_acpi.c

104

I guess we won't need any more entries here unlike the FDT case because

• "SNI ", "SYNQUACR" seems to have enough firmware workarounds to hide the problem
• "AMAZON", "GRAVITON" would need a custom pcie_read_config anyway because the root port is not available via ECAM

sys/dev/pci/pci_host_generic_fdt.c

154

Linux also applies it for socionext,synquacer-pcie-ecam and the SoC-vendor-neutral snps,dw-pcie-ecam

[pan_semihalf.com]

• Rename quirk to PCIE_ECAM_DESIGNWARE_QUIRK
• Add socionext,synquacer-pcie-ecam and snps,dw-pcie-ecam compats

[mw]

LGTM + tested with ACPI and DT on MacchiatoBin.

sys/dev/pci/pci_host_generic_acpi.c

104

Fortunately Marvell version of this IP does not have the necessity of the root port hiding, so it's much simpler. WRT the Amazon version,