qcom_gcc: begin refactoring sys/dev/qcom_gcc to support multiple chipsets

[adrian]

Summary

Although the driver structure is almost supportive of multiple
chipsets, there's a lot of subtle hard coded IPQ4018 assumptions
here.

This is a partial refactor of the driver in order to have a single
qcom_gcc driver that will eventually support multiple chipsets.

• rename qcom_gcc_ipq4018 -> qcom_gcc
• remove the ipq4018 specific naming from things
• create a table to drive probe/attach, with a chipset id to use during attach
• migrate the clock register accessors to not be ipq4018 specific
• migrate the reset register accessors to not be ipq4018 specific

Note this won't compile (yet) for an arm64 kernel because there's
a hard-coded clock tree for an earlier 64 bit MSM part in
sys/arm64/qualcomm/qcom_gcc.c . That will need to be rolled into this
driver.

[phk]

I cant claim much expertise in this area, but I have read the diffs and they look good to me.

[manu]

If you're moving files you might as well move them to sys/dev/clk/qcom

[adrian]

In D49683#1132904, @manu wrote:

If you're moving files you might as well move them to sys/dev/clk/qcom

It's not just a clock controller though, it's /also/ a reset block controller. :-)