riscv: handle misaligned address exceptions

[mhorne]

Summary

If this exception is coming from userspace, send the appropriate SIGBUS
to the process. If it's coming from the kernel this is still fatal, but
we can give a better panic message.

With this, we now handle all defined exception types.

PR: 266109
Found by: syzkaller
Reported by: P1umer <[e-mail]>

[jrtc27]

In theory these should be impossible[1] because firmware is meant to emulate them when not supported. There's nothing wrong with being prepared to handle cases where they aren't emulated but I'm curious in what situations they occur. Maybe misaligned atomics, which can't be safely emulated?

[1] Except on CHERI, as CHERI capabilities have to be stored at aligned locations, so we have this kind of diff downstream for load/store misaligned from userspace, guarded by whether it's a CHERI kernel

[mhorne]

In D36876#837189, @jrtc27 wrote:

In theory these should be impossible[1] because firmware is meant to emulate them when not supported. There's nothing wrong with being prepared to handle cases where they aren't emulated but I'm curious in what situations they occur. Maybe misaligned atomics, which can't be safely emulated?

[1] Except on CHERI, as CHERI capabilities have to be stored at aligned locations, so we have this kind of diff downstream for load/store misaligned from userspace, guarded by whether it's a CHERI kernel

Indeed, misaligned atomics can trigger the panic seen in the report, while normal loads/stores are emulated properly.

[emaste]

looks reasonable to me