Shave off two instructions in save_registers_head

[dg612_cam.ac.uk]

Summary

This patch shaves off up to two three instructions in save_registers_head in exception.S for arm64, which would make more space for instructions that could be added in CheriBSD. This is done by

1. Combining pointer arithmetic with pre-incrementing STP instructions,
2. Removing the instruction that sets the frame pointer (x29) as its content is unused after 05985a7f805f7ac4844c1a246a3822250d411655.

[andrew]

sys/arm64/arm64/exception.S

61

Was there a reason to switch the order of these stores?

68–70

If you move the store of sp & lr first you only need to use one store with write back.

[dg612_cam.ac.uk]

sys/arm64/arm64/exception.S

61

The reason is purely stylistic. Because we need to store x0 and x1 first, it's more natural to then start storing x2, x3, etc.

68–70

Storing sp requires first moving sp into some register, so we have to do it after all registers have already been saved.

[andrew]

sys/arm64/arm64/exception.S

68–70

I mean sp from when the exception was taken. It is already copied to x18.

[dg612_cam.ac.uk]

sys/arm64/arm64/exception.S

68–70

But that only happens when \el == 1, if I understood you correctly?

[andrew]

sys/arm64/arm64/exception.S

68–70

For EL0 sp is loaded from the sp_el0 special register.

[dg612_cam.ac.uk]

sys/arm64/arm64/exception.S

68–70

Yes, but if we put mrs x18, sp_el0 before all the stps, then we would clobber the value of x18 that's being saved?

I suppose another (perhaps better) way is to put -TF_SIZE + before all the st[p|r]s, except for the last one saving x18 and lr, where we use a store with write-back.

[andrew]

sys/arm64/arm64/exception.S

68–70

First in this group of 3 store instructions:

stp x18, lr, [sp, #(TF_SP - TF_X)]!
str x10, [sp, #(TF_ELR)]
stp w11, w12, [sp, #(TF_SPSR)]

[dg612_cam.ac.uk]

sys/arm64/arm64/exception.S

68–70

Oh I completely misunderstood your comment. Yes, it makes total sense to do this. Please see the updated patch.

[andrew]

There was a bug in R10:05985a7f805f for non-DDB users of the unwind code. I have a fix for it in D34711, however it may mean we obly save one instruction in save_registers_head as we will need to keep the update to x29 and bring back another stp to create an AAPCS frame.

[dg612_cam.ac.uk]

In D34631#787885, @andrew wrote:

There was a bug in R10:05985a7f805f for non-DDB users of the unwind code. I have a fix for it in D34711, however it may mean we obly save one instruction in save_registers_head as we will need to keep the update to x29 and bring back another stp to create an AAPCS frame.

That's fine. In fact, saving one instruction is enough to allow me to fit all the CheriBSD-specific instruction into save_registers_head.

Would you be happy to merge this soon?

[andrew]

Can you share a git commit with this change?