The previous update to handle the gicv2m as a child of the gicv3 driver
assumed there was only a single gicv2m child. On some hardware there
are multiple children. Support this by removing the mbi ivars and
adding a new interface to handle MSI allocation in a given range.
Details
Details
- Reviewers
manu - Group Reviewers
ARM arm64 - Commits
- rG18c213949540: Add a gic interface to allocate MSI interrupts
Tested on:
- Parallels with GICv2 & GICv3 + GICv2M
- VMWare Fusion with a GICv3 with MBI
Diff Detail
Diff Detail
- Repository
- rS FreeBSD src repository - subversion
- Lint
Lint Passed - Unit
No Test Coverage - Build Status
Buildable 41842 Build 38730: arc lint + arc unit