Straightforward(ish) port from aesni, without unrolling (block8).
Quick speed test: dd if=/dev/zero of=/dev/md0.eli bs=1m reports ~385 MB/s instead of ~60 MB/s on a Cortex-A72 @ 2GHz (Marvell Armada8k).
Differential D21017
armv8crypto: add AES-XTS support val_packett.cool on Jul 21 2019, 7:19 PM. Authored by Tags Referenced Files
Details
Straightforward(ish) port from aesni, without unrolling (block8). Quick speed test: dd if=/dev/zero of=/dev/md0.eli bs=1m reports ~385 MB/s instead of ~60 MB/s on a Cortex-A72 @ 2GHz (Marvell Armada8k). Tested with opencrypto tests. (D21018 enables them on aarch64)
Diff Detail
Event Timeline
Comment Actions Rebased on top of the crypto rework that just landed (D23677). Implemented crp->crp_cipher_key handling. Comment Actions I'm sorry that this is taking a while to get reviewed. I'd like to help get it in. Would be willing to rebase the patch and re-upload? It doesn't apply for me. Comment Actions Looks fine. You should look at unrolling the loop to 3 or 4 rounds. Looking at the A72 optimization guide, it shows that there is a 3 cycle latency, but throughput of 1. Section 4.10 gives example showing three pairs to achieve max perf. A72 opt guide: Comment Actions It would also be good to test with 'cryptocheck -a all -d armv8crypto0 -z' though the NIST KAT are probably sufficient coverage already for XTS. Comment Actions Hi, I was able to rebase this patch with some very minor tweaks, and verify the results using both cryptocheck and cryptotest.py. Are there any remaining concerns with the patch? I would like to see this committed in the near future. Comment Actions I haven't reviewed the actual XTS bits in armv8_crypto_wrap.c, but the rest all looks good to me. |