arm64: Add explicit barrier after address translation instruction

Following ARMARM sec D5.2.11, which says:

Where an instruction results in an update to a System register,
as is the case with the AT * address translation instructions,
explicit synchronization must be performed before the result is
guaranteed to be visible to subsequent direct reads of the
PAR_EL1.

Reviewed By: andrew
MFC after: 3 weeks
Sponsored by: Ampere Computing
Differential Revision: https://reviews.freebsd.org/D34665