The reset sequence doesn't clear the power down / isolate bits during
power up and configuration. Change that to make sure things are
consistent.
If the PHY is initialised by something external (eg a bootloader,
config EEPROM driving a switch chip, etc) which sets the power down
and/or isolate bits in E1000_CR, then the reset path wouldn't
undo it and the PHY will look permanently down. Even when we
configure autonegotiate or statically nail the port up, it's still
not coming out of the power mode.