uchcom(4): add support for CH9102 and CH343 uarts

[kevlo]

Summary

This patch adds support for CH9102 and CH343 serial adapters.
The WinChipHead CH9102 and CH343 chips support any baud rate up to 6 Mbps.

Test Plan

ugen0.4: <vendor 0x1a86 USB Single Serial> at usbus0
uchcom0 on uhub0
uchcom0: <vendor 0x1a86 USB Single Serial, class 2/0, rev 1.10/4.45, addr 27> on usbus0
uchcom0: CH343 detected

ugen0.4: <vendor 0x1a86 USB2.0-Serial> at usbus0
uchcom0 on uhub0
uchcom0: <vendor 0x1a86 USB2.0-Serial, rev 1.10/2.54, addr 28> on usbus0
uchcom0: CH340 detected

[imp]

I can't test the hardware, nor do I have the hardware spec sheet... but this looks good to my eye...

[kevlo]

Remove unused sc_data_iface_no

[lwhsu]

The only thing I would comment is don't forget to update the .Dd field in manual page. :)

[kevlo]

Bump a date in .Dd field in man page.

[kevlo]

In D46290#1055959, @lwhsu wrote:

The only thing I would comment is don't forget to update the .Dd field in manual page. :)

I missed that, thanks for spotting!

[joerg]

sys/dev/usb/serial/uchcom.c

822

Referring to the discussion in

https://github.com/avrdudes/avrdude/discussions/1639

It seems other BSDs only refuse parity and 5/6/7 bit control for a certain (old) revision of CH340. Do you think it would be possible to implement a somewhat more generic functionality here, rather than restricting it to only CH343?

[kevlo]

Add support for line modes other than 8-bit/no-parity/1-stop on
CH340/CH341 chips.

[kevlo]

sys/dev/usb/serial/uchcom.c

822

The original goal was to support WCH343, but since you asked whether it's
possible to support 5/6/7 data bits, I think it’s feasible.

[kevlo]

sys/dev/usb/serial/uchcom.c

822

The original goal was to support WCH343, but since you asked whether the
CH340/CH341 could support 5/6/7 data bits, I think it’s feasible.
Please try this revised patch, thanks.

[joerg]

sys/dev/usb/serial/uchcom.c

822

Thanks!
I'll try to find a CH340, and give it a try.

[joerg]

I had someone testing the driver, and he told me that the chip is still buffering data.
I made one inline comment where it's a bit suspicious to me about two register write operations that I think got lost now.

sys/dev/usb/serial/uchcom.c

630

Where did those two uchcom_write_reg operations go to in the patched version? I only see a write to UCHCOM_REG_BPS_PRE later on in uchcom_cfg_open(), but only to a default configuration.