It is more natural for these values which are infrequently read, but may be frequently updated.
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I was about to comment that other pmaps still use atomics for these counters, but it seems that amd64's also been using counter(9) for a while. I'm a bit skeptical that that's really necessary (except perhaps for p_failures), but it doesn't have much downside either. It would be nice to make at least arm64 consistent.
I share your skepticism for the L2 counters, but I see no real harm in this change. Similarly, I would have no objections to making the same change on arm64. On arm64, we are using counter(9) for 64KB pages, where the counts are typically two orders of magnitude larger.
Does anyone know if any real riscv hardware implements their extension that supports additional page sizes, particularly, 64KB?
Yes, the unstated motivation here is to follow amd64. I will follow-up with the change for arm64.
There is no hardware implementing this at present, just the simulators :(