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arm64, qoriq_therm: fix handling sites on version 1 and 2
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Authored by bz on Jul 10 2022, 1:46 PM.
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Details

Summary

For version 2 extend the TMUV2_TMSAR() write loop over all site_ids
registered for a particular SoC and actually use the site_id rather
than always just the first [0] (which for the LX2080 would be a
problem given there is no site0).

Later, while version 2 adds the SITEs to enable to TMSR in bits 0..<n>,
version 1 (e.g., LS1028, LS1046, LS1088) add MSITEs to TMR
bits 16..31 or rather 15..0(16-<n>). Adjust the loops to only enable
the site_ids listed for the particular SoC for monitoring. This now
also deals with sparse site_ids (not starting at 0, or not being
contiguous).

MFC after: 2 weeks

Test Plan

On my LS1088 I am getting temperatures instead of timeouts now:

root@ten64-01:~ # sysctl hw.temperature
hw.temperature.core-cluster: 58.0C
hw.temperature.soc: 57.0C

Diff Detail

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Event Timeline

bz requested review of this revision.Jul 10 2022, 1:46 PM

Fix version 1 and 2 bits in loops for site_ids.

bz retitled this revision from arm64, qoriq_therm: fix enabling sites on version 1 to arm64, qoriq_therm: fix handling sites on version 1 and 2.Jul 15 2022, 2:06 PM
bz edited the summary of this revision. (Show Details)
mmel added inline comments.
sys/arm64/qoriq/qoriq_therm.c
452

Only small nit: This cycle is common to both versions so it can be moved before if ().
But if you prefer this version commit it, I'm fine with both variants

This revision is now accepted and ready to land.Jul 16 2022, 6:58 AM
sys/arm64/qoriq/qoriq_therm.c
452

If I move the for out then I have to always branch inside the the loop; would be possible if it wasn't 1 << (15 - x) vs. 1 << x for building up the "sites".
Unless I miss something...