According to description of the Data In Polarity register,
configuring pin's corresponding bit to '1' inverts the
value its input. Hitherto configuration during attach
unconditionally set the invertion for each GPIO pin.
Fix that.
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Can you please try the test again with https://cgit.FreeBSD.org/src/commit/?id=ce5a4083de2d79bc44d209c9e355a09ede47346c ? I hope that it fixed also this problem. Thanks.
The fix does not help for observed issue. I get almost 100% hang rate on PCIE init on McBin when booting with DT from U-Boot and EDK2.
It will boot further 100% times with the GPIO driver probe disabled. I'll update this patch and add another GPIO driver fix - with those McBin passed 100x boot loop test.
PCIE hang example of pure today's HEAD:
https://gist.github.com/semihalf-wojtas-marcin/fd8ac0059aab12299b0d174aca5eaed6
Boot with the GPIO fixes (this patch + https://reviews.freebsd.org/D29013). Note, there are no ICU update, hence CP110 MMC timeout:
https://gist.github.com/semihalf-wojtas-marcin/04c1283b8b381760f8ad11b656c5d918
Testing showed, more changes are needed compared to v1. Now the pin configuration can be done only on purpose (which aligns the behavior to Linux).
I don't think this change is necessary (it mitigates another bug). So I prefer to unconditionally initialize both registers in attach.
I can agree for blink register, but inverting data in polarity for each pin is imo not good idea. I'll update the patch.