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[PowerPC] Kernel 64-bit atomics emulation for PPC32
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Authored by bdragon on Dec 30 2019, 10:22 PM.
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Details

Summary

Here is the kernel side of the 64-bit atomics emulation needed for D22827 and other optimizations.

jhibbits did the main work, this is just a cleanup and split to kernel-side only.

Tested on an iBook G4 with D22827 applied.

Test Plan
  • Excercise all atomics from a test module?

Diff Detail

Repository
rS FreeBSD src repository - subversion
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Unit
Tests Not Applicable

Event Timeline

sys/kern/subr_atomic64.c
1 ↗(On Diff #66165)

Since this is being done only for powerpc, should this not be moved to sys/powerpc/powerpc instead?

sys/sys/_atomic64e.h
1 ↗(On Diff #66165)

Same as above for this. And then it could be moved into sys/powerpc/include/atomic.h even.

sys/sys/_atomic64e.h
1 ↗(On Diff #66165)

I think it's not unlikely that some other 32bit platform may find it useful.

If it makes sense to move them to sys/powerpc later, we can do that.

sys/sys/_atomic64e.h
1 ↗(On Diff #66165)

I agree. But if none others will make use of them (I've heard mips32 is UP only, so would probably take a much different route for atomic64), it doesn't make sense to keep it generic.

But, I won't block the review on that.

This revision is now accepted and ready to land.Jan 2 2020, 6:48 PM

I'd add Kyle Evans to this review.
Mips32 does have SMP, but the specific core has 64bit atomics if anybody wants to revive it.

sys/kern/subr_atomic64.c
1 ↗(On Diff #66165)

Kyle is working on this for mips32 too...

sys/sys/_atomic64e.h
39 ↗(On Diff #66165)

Maybe rename this to HAS_EMULATED_ATOMIC64 or something like that since we'll use it for mips, too.

jeff added inline comments.
sys/kern/subr_atomic64.c
57 ↗(On Diff #66165)

There is alright a macro for this. CACHE_LINE_SIZE

sys/sys/_atomic64e.h
44 ↗(On Diff #66165)

These declarations should also be included in the above _KERNEL check to hide them from userland

sys/kern/subr_atomic64.c
57 ↗(On Diff #66165)

We need to make sure this can be option in kernel config file... unless CACHE LINE SIZE already does that...