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riscv: Fix SSTC extension support

Description

riscv: Fix SSTC extension support

From the SSTC spec:
"If the stimecmp (supervisor-mode timer compare) register is implemented,
then STIP is read-only in mip and reflects the supervisor-level timer
interrupt signal resulting from stimecmp. This timer interrupt signal
is cleared by writing stimecmp with a value greater than the current time
value."

This fixes operation in Spike with sstc extension enabled.
Example:

spike --isa RV64IMAFDCH_zicntr_zihpm_sstc

Reviewed by: mhorne
Differential Revision: https://reviews.freebsd.org/D45226

Details

Provenance
brAuthored on May 22 2024, 2:51 PM
Reviewer
mhorne
Differential Revision
D45226: Fix SSTC extension support
Parents
rGbea2bf458d2c: tpm_if.m: declare bus addresses as bus_size_t not bus_addr_t
Branches
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