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sdhci_fsl_fdt: specify base clk divisor per SoC

Description

sdhci_fsl_fdt: specify base clk divisor per SoC

Only LS1046A and LS1028A require the base clk to be divided by 2.
Implement that by moving the divider to a SoC specific data.
This commit fixes base clk setup for the entire SoC family,
including the already suported LS2160A.

Submitted by: Lukasz Hajec <lha@semihalf.com>
Reviewed by: manu
Obtained from: Semihalf
Sponsored by: Alstom Group
Differential Revision: https://reviews.freebsd.org/D30120

Details

Provenance
mwAuthored on May 7 2021, 1:45 AM
Reviewer
manu
Differential Revision
D30120: sdhci_fsl_fdt.c: Specify base clk divisor per SoC.
Parents
rG4dfb620ea4a7: Add LS1028A clockgen driver
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