Allow I/OAT of present Xeon E5/E7 to work thorugh PLX NTB.
Its a hack, we can't know/list all DMA engines, but this covers all
I/OAT of Xeon E5/E7 at least from Sandy Bridge till Skylake I saw.
MFC after: 1 week
Sponsored by: iXsystems, Inc.
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mav Authored on Feb 21 2019, 2:10 PM - Parents
- rG560c058683bd: The receive buffer autoscaling for TCP is based on a linear growth, which
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