[PowerPC64] Clear low-order bits of ARPN

PowerISA 2.07B says that the low-order p-12 bits of the real page number
contained in ARPN and LP fields of a PTE must be 0s and are ignored
by the hardware (Book III-S, 5.7.7.1), where 2^p is the actual page size
in bytes, but we were clearing only the LP field.

This worked on bare metal and QEMU with KVM, that ignore these bits,
but caused a kernel panic on QEMU with TCG, that expects them to be
cleared.

This fixes running FreeBSD with HPT superpages enabled on QEMU
with TCG.

MFC after: 2 weeks
Sponsored by: Eldorado Research Institute (eldorado.org.br)