D6211.diff
No OneTemporary
Actions

Size

191 KB

Referenced Files

None

Subscribers

None

D6211.diff
View Options

	Index: head/sys/dev/ixl/i40e_adminq.c
	===================================================================
	--- head/sys/dev/ixl/i40e_adminq.c
	+++ head/sys/dev/ixl/i40e_adminq.c
	@@ -496,8 +496,12 @@
	{
	enum i40e_status_code ret_code = I40E_SUCCESS;

	- if (hw->aq.asq.count == 0)
	- return I40E_ERR_NOT_READY;
	+ i40e_acquire_spinlock(&hw->aq.asq_spinlock);
	+
	+ if (hw->aq.asq.count == 0) {
	+ ret_code = I40E_ERR_NOT_READY;
	+ goto shutdown_asq_out;
	+ }

	/* Stop firmware AdminQ processing */
	wr32(hw, hw->aq.asq.head, 0);
	@@ -506,16 +510,13 @@
	wr32(hw, hw->aq.asq.bal, 0);
	wr32(hw, hw->aq.asq.bah, 0);

	- /* make sure spinlock is available */
	- i40e_acquire_spinlock(&hw->aq.asq_spinlock);
	-
	hw->aq.asq.count = 0; /* to indicate uninitialized queue */

	/* free ring buffers */
	i40e_free_asq_bufs(hw);

	+shutdown_asq_out:
	i40e_release_spinlock(&hw->aq.asq_spinlock);
	-
	return ret_code;
	}

	@@ -529,8 +530,12 @@
	{
	enum i40e_status_code ret_code = I40E_SUCCESS;

	- if (hw->aq.arq.count == 0)
	- return I40E_ERR_NOT_READY;
	+ i40e_acquire_spinlock(&hw->aq.arq_spinlock);
	+
	+ if (hw->aq.arq.count == 0) {
	+ ret_code = I40E_ERR_NOT_READY;
	+ goto shutdown_arq_out;
	+ }

	/* Stop firmware AdminQ processing */
	wr32(hw, hw->aq.arq.head, 0);
	@@ -539,16 +544,13 @@
	wr32(hw, hw->aq.arq.bal, 0);
	wr32(hw, hw->aq.arq.bah, 0);

	- /* make sure spinlock is available */
	- i40e_acquire_spinlock(&hw->aq.arq_spinlock);
	-
	hw->aq.arq.count = 0; /* to indicate uninitialized queue */

	/* free ring buffers */
	i40e_free_arq_bufs(hw);

	+shutdown_arq_out:
	i40e_release_spinlock(&hw->aq.arq_spinlock);
	-
	return ret_code;
	}

	@@ -773,21 +775,23 @@
	u16 retval = 0;
	u32 val = 0;

	+ i40e_acquire_spinlock(&hw->aq.asq_spinlock);
	+
	hw->aq.asq_last_status = I40E_AQ_RC_OK;

	- val = rd32(hw, hw->aq.asq.head);
	- if (val >= hw->aq.num_asq_entries) {
	+ if (hw->aq.asq.count == 0) {
	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
	- "AQTX: head overrun at %d\n", val);
	+ "AQTX: Admin queue not initialized.\n");
	status = I40E_ERR_QUEUE_EMPTY;
	- goto asq_send_command_exit;
	+ goto asq_send_command_error;
	}

	- if (hw->aq.asq.count == 0) {
	+ val = rd32(hw, hw->aq.asq.head);
	+ if (val >= hw->aq.num_asq_entries) {
	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
	- "AQTX: Admin queue not initialized.\n");
	+ "AQTX: head overrun at %d\n", val);
	status = I40E_ERR_QUEUE_EMPTY;
	- goto asq_send_command_exit;
	+ goto asq_send_command_error;
	}

	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
	@@ -817,8 +821,6 @@
	desc->flags &= ~CPU_TO_LE16(details->flags_dis);
	desc->flags \|= CPU_TO_LE16(details->flags_ena);

	- i40e_acquire_spinlock(&hw->aq.asq_spinlock);
	-
	if (buff_size > hw->aq.asq_buf_size) {
	i40e_debug(hw,
	I40E_DEBUG_AQ_MESSAGE,
	@@ -948,7 +950,6 @@

	asq_send_command_error:
	i40e_release_spinlock(&hw->aq.asq_spinlock);
	-asq_send_command_exit:
	return status;
	}

	Index: head/sys/dev/ixl/i40e_adminq_cmd.h
	===================================================================
	--- head/sys/dev/ixl/i40e_adminq_cmd.h
	+++ head/sys/dev/ixl/i40e_adminq_cmd.h
	@@ -42,11 +42,7 @@
	*/

	#define I40E_FW_API_VERSION_MAJOR 0x0001
	-#ifdef X722_SUPPORT
	-#define I40E_FW_API_VERSION_MINOR 0x0003
	-#else
	#define I40E_FW_API_VERSION_MINOR 0x0004
	-#endif

	struct i40e_aq_desc {
	__le16 flags;
	@@ -270,12 +266,6 @@
	/* Tunnel commands */
	i40e_aqc_opc_add_udp_tunnel = 0x0B00,
	i40e_aqc_opc_del_udp_tunnel = 0x0B01,
	-#ifdef X722_SUPPORT
	- i40e_aqc_opc_set_rss_key = 0x0B02,
	- i40e_aqc_opc_set_rss_lut = 0x0B03,
	- i40e_aqc_opc_get_rss_key = 0x0B04,
	- i40e_aqc_opc_get_rss_lut = 0x0B05,
	-#endif

	/* Async Events */
	i40e_aqc_opc_event_lan_overflow = 0x1001,
	@@ -840,16 +830,8 @@
	I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
	/* queueing option section */
	u8 queueing_opt_flags;
	-#ifdef X722_SUPPORT
	-#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
	-#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
	-#endif
	#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
	#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
	-#ifdef X722_SUPPORT
	-#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
	-#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
	-#endif
	u8 queueing_opt_reserved[3];
	/* scheduler section */
	u8 up_enable_bits;
	@@ -2155,7 +2137,13 @@
	*/
	struct i40e_aqc_lldp_set_local_mib {
	#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
	-#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
	+#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
	+ SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
	+#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
	+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
	+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
	+ SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
	+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
	u8 type;
	u8 reserved0;
	__le16 length;
	@@ -2221,48 +2209,6 @@
	};

	I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
	-#ifdef X722_SUPPORT
	-
	-struct i40e_aqc_get_set_rss_key {
	-#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
	-#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
	-#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
	- I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
	- __le16 vsi_id;
	- u8 reserved[6];
	- __le32 addr_high;
	- __le32 addr_low;
	-};
	-
	-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
	-
	-struct i40e_aqc_get_set_rss_key_data {
	- u8 standard_rss_key[0x28];
	- u8 extended_hash_key[0xc];
	-};
	-
	-I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
	-
	-struct i40e_aqc_get_set_rss_lut {
	-#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
	-#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
	-#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
	- I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
	- __le16 vsi_id;
	-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
	-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
	- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
	-
	-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
	-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
	- __le16 flags;
	- u8 reserved[4];
	- __le32 addr_high;
	- __le32 addr_low;
	-};
	-
	-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
	-#endif

	/* tunnel key structure 0x0B10 */

	Index: head/sys/dev/ixl/i40e_alloc.h
	===================================================================
	--- head/sys/dev/ixl/i40e_alloc.h
	+++ head/sys/dev/ixl/i40e_alloc.h
	@@ -1,6 +1,6 @@
	/******************************************************************************

	- Copyright (c) 2013-2014, Intel Corporation
	+ Copyright (c) 2013-2015, Intel Corporation
	All rights reserved.

	Redistribution and use in source and binary forms, with or without
	Index: head/sys/dev/ixl/i40e_common.c
	===================================================================
	--- head/sys/dev/ixl/i40e_common.c
	+++ head/sys/dev/ixl/i40e_common.c
	@@ -67,19 +67,6 @@
	case I40E_DEV_ID_20G_KR2_A:
	hw->mac.type = I40E_MAC_XL710;
	break;
	-#ifdef X722_SUPPORT
	- case I40E_DEV_ID_SFP_X722:
	- case I40E_DEV_ID_1G_BASE_T_X722:
	- case I40E_DEV_ID_10G_BASE_T_X722:
	- hw->mac.type = I40E_MAC_X722;
	- break;
	-#endif
	-#ifdef X722_SUPPORT
	- case I40E_DEV_ID_X722_VF:
	- case I40E_DEV_ID_X722_VF_HV:
	- hw->mac.type = I40E_MAC_X722_VF;
	- break;
	-#endif
	case I40E_DEV_ID_VF:
	case I40E_DEV_ID_VF_HV:
	hw->mac.type = I40E_MAC_VF;
	@@ -102,7 +89,7 @@
	* @hw: pointer to the HW structure
	* @aq_err: the AQ error code to convert
	**/
	-char i40e_aq_str(struct i40e_hw hw, enum i40e_admin_queue_err aq_err)
	+const char i40e_aq_str(struct i40e_hw hw, enum i40e_admin_queue_err aq_err)
	{
	switch (aq_err) {
	case I40E_AQ_RC_OK:
	@@ -162,7 +149,7 @@
	* @hw: pointer to the HW structure
	* @stat_err: the status error code to convert
	**/
	-char i40e_stat_str(struct i40e_hw hw, enum i40e_status_code stat_err)
	+const char i40e_stat_str(struct i40e_hw hw, enum i40e_status_code stat_err)
	{
	switch (stat_err) {
	case I40E_SUCCESS:
	@@ -409,171 +396,6 @@

	return status;
	}
	-#ifdef X722_SUPPORT
	-
	-/**
	- * i40e_aq_get_set_rss_lut
	- * @hw: pointer to the hardware structure
	- * @vsi_id: vsi fw index
	- * @pf_lut: for PF table set TRUE, for VSI table set FALSE
	- * @lut: pointer to the lut buffer provided by the caller
	- * @lut_size: size of the lut buffer
	- * @set: set TRUE to set the table, FALSE to get the table
	- *
	- * Internal function to get or set RSS look up table
	- **/
	-static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
	- u16 vsi_id, bool pf_lut,
	- u8 *lut, u16 lut_size,
	- bool set)
	-{
	- enum i40e_status_code status;
	- struct i40e_aq_desc desc;
	- struct i40e_aqc_get_set_rss_lut *cmd_resp =
	- (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
	-
	- if (set)
	- i40e_fill_default_direct_cmd_desc(&desc,
	- i40e_aqc_opc_set_rss_lut);
	- else
	- i40e_fill_default_direct_cmd_desc(&desc,
	- i40e_aqc_opc_get_rss_lut);
	-
	- /* Indirect command */
	- desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
	- desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
	-
	- cmd_resp->vsi_id =
	- CPU_TO_LE16((u16)((vsi_id <<
	- I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
	- I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
	- cmd_resp->vsi_id \|= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
	-
	- if (pf_lut)
	- cmd_resp->flags \|= CPU_TO_LE16((u16)
	- ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
	- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
	- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
	- else
	- cmd_resp->flags \|= CPU_TO_LE16((u16)
	- ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
	- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
	- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
	-
	- cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)lut));
	- cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)lut));
	-
	- status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
	-
	- return status;
	-}
	-
	-/**
	- * i40e_aq_get_rss_lut
	- * @hw: pointer to the hardware structure
	- * @vsi_id: vsi fw index
	- * @pf_lut: for PF table set TRUE, for VSI table set FALSE
	- * @lut: pointer to the lut buffer provided by the caller
	- * @lut_size: size of the lut buffer
	- *
	- * get the RSS lookup table, PF or VSI type
	- **/
	-enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
	- bool pf_lut, u8 *lut, u16 lut_size)
	-{
	- return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
	- FALSE);
	-}
	-
	-/**
	- * i40e_aq_set_rss_lut
	- * @hw: pointer to the hardware structure
	- * @vsi_id: vsi fw index
	- * @pf_lut: for PF table set TRUE, for VSI table set FALSE
	- * @lut: pointer to the lut buffer provided by the caller
	- * @lut_size: size of the lut buffer
	- *
	- * set the RSS lookup table, PF or VSI type
	- **/
	-enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
	- bool pf_lut, u8 *lut, u16 lut_size)
	-{
	- return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
	-}
	-
	-/**
	- * i40e_aq_get_set_rss_key
	- * @hw: pointer to the hw struct
	- * @vsi_id: vsi fw index
	- * @key: pointer to key info struct
	- * @set: set TRUE to set the key, FALSE to get the key
	- *
	- * get the RSS key per VSI
	- **/
	-static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
	- u16 vsi_id,
	- struct i40e_aqc_get_set_rss_key_data *key,
	- bool set)
	-{
	- enum i40e_status_code status;
	- struct i40e_aq_desc desc;
	- struct i40e_aqc_get_set_rss_key *cmd_resp =
	- (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
	- u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
	-
	- if (set)
	- i40e_fill_default_direct_cmd_desc(&desc,
	- i40e_aqc_opc_set_rss_key);
	- else
	- i40e_fill_default_direct_cmd_desc(&desc,
	- i40e_aqc_opc_get_rss_key);
	-
	- /* Indirect command */
	- desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
	- desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
	-
	- cmd_resp->vsi_id =
	- CPU_TO_LE16((u16)((vsi_id <<
	- I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
	- I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
	- cmd_resp->vsi_id \|= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
	- cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)key));
	- cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)key));
	-
	- status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
	-
	- return status;
	-}
	-
	-/**
	- * i40e_aq_get_rss_key
	- * @hw: pointer to the hw struct
	- * @vsi_id: vsi fw index
	- * @key: pointer to key info struct
	- *
	- **/
	-enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
	- u16 vsi_id,
	- struct i40e_aqc_get_set_rss_key_data *key)
	-{
	- return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
	-}
	-
	-/**
	- * i40e_aq_set_rss_key
	- * @hw: pointer to the hw struct
	- * @vsi_id: vsi fw index
	- * @key: pointer to key info struct
	- *
	- * set the RSS key per VSI
	- **/
	-enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
	- u16 vsi_id,
	- struct i40e_aqc_get_set_rss_key_data *key)
	-{
	- return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
	-}
	-#endif /* X722_SUPPORT */

	/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
	* hardware to a bit-field that can be used by SW to more easily determine the
	@@ -988,9 +810,6 @@

	switch (hw->mac.type) {
	case I40E_MAC_XL710:
	-#ifdef X722_SUPPORT
	- case I40E_MAC_X722:
	-#endif
	break;
	default:
	return I40E_ERR_DEVICE_NOT_SUPPORTED;
	@@ -1626,6 +1445,9 @@
	if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
	status = I40E_ERR_UNKNOWN_PHY;

	+ if (report_init)
	+ hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
	+
	return status;
	}

	@@ -5218,7 +5040,7 @@

	cmd_resp->address = CPU_TO_LE32(addr);
	cmd_resp->length = CPU_TO_LE32(dw_count);
	- cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
	+ cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
	cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));

	status = i40e_asq_send_command(hw, &desc, buffer,
	Index: head/sys/dev/ixl/i40e_devids.h
	===================================================================
	--- head/sys/dev/ixl/i40e_devids.h
	+++ head/sys/dev/ixl/i40e_devids.h
	@@ -53,13 +53,6 @@
	#define I40E_DEV_ID_10G_BASE_T4 0x1589
	#define I40E_DEV_ID_VF 0x154C
	#define I40E_DEV_ID_VF_HV 0x1571
	-#ifdef X722_SUPPORT
	-#define I40E_DEV_ID_SFP_X722 0x37D0
	-#define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
	-#define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
	-#define I40E_DEV_ID_X722_VF 0x37CD
	-#define I40E_DEV_ID_X722_VF_HV 0x37D9
	-#endif /* X722_SUPPORT */

	#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A \|\| \
	(d) == I40E_DEV_ID_QSFP_B \|\| \
	Index: head/sys/dev/ixl/i40e_hmc.c
	===================================================================
	--- head/sys/dev/ixl/i40e_hmc.c
	+++ head/sys/dev/ixl/i40e_hmc.c
	@@ -37,9 +37,7 @@
	#include "i40e_status.h"
	#include "i40e_alloc.h"
	#include "i40e_hmc.h"
	-#ifndef I40E_NO_TYPE_HEADER
	#include "i40e_type.h"
	-#endif

	/**
	* i40e_add_sd_table_entry - Adds a segment descriptor to the table
	Index: head/sys/dev/ixl/i40e_lan_hmc.h
	===================================================================
	--- head/sys/dev/ixl/i40e_lan_hmc.h
	+++ head/sys/dev/ixl/i40e_lan_hmc.h
	@@ -1,6 +1,6 @@
	/******************************************************************************

	- Copyright (c) 2013-2014, Intel Corporation
	+ Copyright (c) 2013-2015, Intel Corporation
	All rights reserved.

	Redistribution and use in source and binary forms, with or without
	Index: head/sys/dev/ixl/i40e_nvm.c
	===================================================================
	--- head/sys/dev/ixl/i40e_nvm.c
	+++ head/sys/dev/ixl/i40e_nvm.c
	@@ -218,10 +218,6 @@
	enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
	u16 *data)
	{
	-#ifdef X722_SUPPORT
	- if (hw->mac.type == I40E_MAC_X722)
	- return i40e_read_nvm_word_aq(hw, offset, data);
	-#endif
	return i40e_read_nvm_word_srctl(hw, offset, data);
	}

	@@ -310,10 +306,6 @@
	enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
	u16 words, u16 data)
	{
	-#ifdef X722_SUPPORT
	- if (hw->mac.type == I40E_MAC_X722)
	- return i40e_read_nvm_buffer_aq(hw, offset, words, data);
	-#endif
	return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
	}

	Index: head/sys/dev/ixl/i40e_osdep.c
	===================================================================
	--- head/sys/dev/ixl/i40e_osdep.c
	+++ head/sys/dev/ixl/i40e_osdep.c
	@@ -1,6 +1,6 @@
	/******************************************************************************

	- Copyright (c) 2013-2014, Intel Corporation
	+ Copyright (c) 2013-2015, Intel Corporation
	All rights reserved.

	Redistribution and use in source and binary forms, with or without
	Index: head/sys/dev/ixl/i40e_prototype.h
	===================================================================
	--- head/sys/dev/ixl/i40e_prototype.h
	+++ head/sys/dev/ixl/i40e_prototype.h
	@@ -78,21 +78,8 @@
	void i40e_resume_aq(struct i40e_hw *hw);
	bool i40e_check_asq_alive(struct i40e_hw *hw);
	enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
	-#ifdef X722_SUPPORT
	-
	-enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
	- bool pf_lut, u8 *lut, u16 lut_size);
	-enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,
	- bool pf_lut, u8 *lut, u16 lut_size);
	-enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
	- u16 seid,
	- struct i40e_aqc_get_set_rss_key_data *key);
	-enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
	- u16 seid,
	- struct i40e_aqc_get_set_rss_key_data *key);
	-#endif
	-char i40e_aq_str(struct i40e_hw hw, enum i40e_admin_queue_err aq_err);
	-char i40e_stat_str(struct i40e_hw hw, enum i40e_status_code stat_err);
	+const char i40e_aq_str(struct i40e_hw hw, enum i40e_admin_queue_err aq_err);
	+const char i40e_stat_str(struct i40e_hw hw, enum i40e_status_code stat_err);


	u32 i40e_led_get(struct i40e_hw *hw);
	Index: head/sys/dev/ixl/i40e_register.h
	===================================================================
	--- head/sys/dev/ixl/i40e_register.h
	+++ head/sys/dev/ixl/i40e_register.h
	@@ -3382,1936 +3382,4 @@
	#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
	#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
	#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
	-#ifdef X722_SUPPORT
	-
	-#define I40E_MNGSB_FDCRC 0x000B7050 /* Reset: POR */
	-#define I40E_MNGSB_FDCRC_CRC_RES_SHIFT 0
	-#define I40E_MNGSB_FDCRC_CRC_RES_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCRC_CRC_RES_SHIFT)
	-#define I40E_MNGSB_FDCS 0x000B7040 /* Reset: POR */
	-#define I40E_MNGSB_FDCS_CRC_CONT_SHIFT 2
	-#define I40E_MNGSB_FDCS_CRC_CONT_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_CONT_SHIFT)
	-#define I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT 3
	-#define I40E_MNGSB_FDCS_CRC_SEED_EN_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT)
	-#define I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT 4
	-#define I40E_MNGSB_FDCS_CRC_WR_INH_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT)
	-#define I40E_MNGSB_FDCS_CRC_SEED_SHIFT 8
	-#define I40E_MNGSB_FDCS_CRC_SEED_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCS_CRC_SEED_SHIFT)
	-#define I40E_MNGSB_FDS 0x000B7048 /* Reset: POR */
	-#define I40E_MNGSB_FDS_START_BC_SHIFT 0
	-#define I40E_MNGSB_FDS_START_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_START_BC_SHIFT)
	-#define I40E_MNGSB_FDS_LAST_BC_SHIFT 16
	-#define I40E_MNGSB_FDS_LAST_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_LAST_BC_SHIFT)
	-
	-#define I40E_GL_VF_CTRL_RX(_VF) (0x00083600 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	-#define I40E_GL_VF_CTRL_RX_MAX_INDEX 127
	-#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT 0
	-#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT)
	-#define I40E_GL_VF_CTRL_TX(_VF) (0x00083400 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	-#define I40E_GL_VF_CTRL_TX_MAX_INDEX 127
	-#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT 0
	-#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT)
	-
	-#define I40E_GLCM_LAN_CACHESIZE 0x0010C4D8 /* Reset: CORER */
	-#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT 0
	-#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT)
	-#define I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT 12
	-#define I40E_GLCM_LAN_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT)
	-#define I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT 16
	-#define I40E_GLCM_LAN_CACHESIZE_WAYS_MASK I40E_MASK(0x3FF, I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT)
	-#define I40E_GLCM_PE_CACHESIZE 0x00138FE4 /* Reset: CORER */
	-#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT 0
	-#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT)
	-#define I40E_GLCM_PE_CACHESIZE_SETS_SHIFT 12
	-#define I40E_GLCM_PE_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_PE_CACHESIZE_SETS_SHIFT)
	-#define I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT 16
	-#define I40E_GLCM_PE_CACHESIZE_WAYS_MASK I40E_MASK(0x1FF, I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT)
	-#define I40E_PFCM_PE_ERRDATA 0x00138D00 /* Reset: PFR */
	-#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
	-#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
	-#define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
	-#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT)
	-#define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8
	-#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT)
	-#define I40E_PFCM_PE_ERRINFO 0x00138C80 /* Reset: PFR */
	-#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
	-#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
	-#define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
	-#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT)
	-#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
	-#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
	-#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
	-#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
	-#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
	-#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
	-
	-#define I40E_PRTDCB_TFMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 / / Reset: CORER */
	-#define I40E_PRTDCB_TFMSTC_MAX_INDEX 7
	-#define I40E_PRTDCB_TFMSTC_MSTC_SHIFT 0
	-#define I40E_PRTDCB_TFMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TFMSTC_MSTC_SHIFT)
	-#define I40E_GL_FWSTS_FWROWD_SHIFT 8
	-#define I40E_GL_FWSTS_FWROWD_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWROWD_SHIFT)
	-#define I40E_GLFOC_CACHESIZE 0x000AA0DC /* Reset: CORER */
	-#define I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT 0
	-#define I40E_GLFOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT)
	-#define I40E_GLFOC_CACHESIZE_SETS_SHIFT 8
	-#define I40E_GLFOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLFOC_CACHESIZE_SETS_SHIFT)
	-#define I40E_GLFOC_CACHESIZE_WAYS_SHIFT 20
	-#define I40E_GLFOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLFOC_CACHESIZE_WAYS_SHIFT)
	-#define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15
	-#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
	-#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
	-#define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_CEQPART_MAX_INDEX 15
	-#define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0
	-#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT)
	-#define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16
	-#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT)
	-#define I40E_GLHMC_DBCQMAX 0x000C20F0 /* Reset: CORER */
	-#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT 0
	-#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_MASK I40E_MASK(0x3FFFF, I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT)
	-#define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_DBCQPART_MAX_INDEX 15
	-#define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0
	-#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT)
	-#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16
	-#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT)
	-#define I40E_GLHMC_DBQPMAX 0x000C20EC /* Reset: CORER */
	-#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT 0
	-#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_MASK I40E_MASK(0x7FFFF, I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT)
	-#define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_DBQPPART_MAX_INDEX 15
	-#define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0
	-#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT)
	-#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16
	-#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT)
	-#define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEARPBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0
	-#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT)
	-#define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEARPCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0
	-#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT)
	-#define I40E_GLHMC_PEARPMAX 0x000C2038 /* Reset: CORER */
	-#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0
	-#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT)
	-#define I40E_GLHMC_PEARPOBJSZ 0x000C2034 /* Reset: CORER */
	-#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0
	-#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK I40E_MASK(0x7, I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT)
	-#define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PECQBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0
	-#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT)
	-#define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PECQCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0
	-#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT)
	-#define I40E_GLHMC_PECQOBJSZ 0x000C2020 /* Reset: CORER */
	-#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0
	-#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT)
	-#define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEHTCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0
	-#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT)
	-#define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0
	-#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT)
	-#define I40E_GLHMC_PEHTEOBJSZ 0x000C202c /* Reset: CORER */
	-#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0
	-#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT)
	-#define I40E_GLHMC_PEHTMAX 0x000C2030 /* Reset: CORER */
	-#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0
	-#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK I40E_MASK(0x1FFFFF, I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT)
	-#define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEMRBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0
	-#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT)
	-#define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEMRCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0
	-#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT)
	-#define I40E_GLHMC_PEMRMAX 0x000C2040 /* Reset: CORER */
	-#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0
	-#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT)
	-#define I40E_GLHMC_PEMROBJSZ 0x000C203c /* Reset: CORER */
	-#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0
	-#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT)
	-#define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0
	-#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT)
	-#define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0
	-#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT)
	-#define I40E_GLHMC_PEPBLMAX 0x000C206c /* Reset: CORER */
	-#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0
	-#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT)
	-#define I40E_GLHMC_PEPFFIRSTSD 0x000C20E4 /* Reset: CORER */
	-#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT 0
	-#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_MASK I40E_MASK(0xFFF, I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT)
	-#define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0
	-#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT)
	-#define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15
	-#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0
	-#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT)
	-#define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
	-#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
	-#define I40E_GLHMC_PEQ1FLMAX 0x000C2058 /* Reset: CORER */
	-#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0
	-#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
	-#define I40E_GLHMC_PEQ1MAX 0x000C2054 /* Reset: CORER */
	-#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0
	-#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
	-#define I40E_GLHMC_PEQ1OBJSZ 0x000C2050 /* Reset: CORER */
	-#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0
	-#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT)
	-#define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEQPBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0
	-#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT)
	-#define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEQPCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0
	-#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT)
	-#define I40E_GLHMC_PEQPOBJSZ 0x000C201c /* Reset: CORER */
	-#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0
	-#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT)
	-#define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PESRQBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0
	-#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT)
	-#define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PESRQCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0
	-#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT)
	-#define I40E_GLHMC_PESRQMAX 0x000C2028 /* Reset: CORER */
	-#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0
	-#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT)
	-#define I40E_GLHMC_PESRQOBJSZ 0x000C2024 /* Reset: CORER */
	-#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0
	-#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT)
	-#define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0
	-#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT)
	-#define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0
	-#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT)
	-#define I40E_GLHMC_PETIMERMAX 0x000C2084 /* Reset: CORER */
	-#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0
	-#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT)
	-#define I40E_GLHMC_PETIMEROBJSZ 0x000C2080 /* Reset: CORER */
	-#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0
	-#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT)
	-#define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEXFBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0
	-#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT)
	-#define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEXFCNT_MAX_INDEX 15
	-#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0
	-#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT)
	-#define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15
	-#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
	-#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT)
	-#define I40E_GLHMC_PEXFFLMAX 0x000C204c /* Reset: CORER */
	-#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0
	-#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK I40E_MASK(0x1FFFFFF, I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
	-#define I40E_GLHMC_PEXFMAX 0x000C2048 /* Reset: CORER */
	-#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
	-#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
	-#define I40E_GLHMC_PEXFOBJSZ 0x000C2044 /* Reset: CORER */
	-#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0
	-#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT)
	-#define I40E_GLHMC_PFPESDPART(_i) (0x000C0880 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLHMC_PFPESDPART_MAX_INDEX 15
	-#define I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT 0
	-#define I40E_GLHMC_PFPESDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT)
	-#define I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT 16
	-#define I40E_GLHMC_PFPESDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT)
	-#define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
	-#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
	-#define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFCEQPART_MAX_INDEX 31
	-#define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0
	-#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT)
	-#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16
	-#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT)
	-#define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31
	-#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0
	-#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT)
	-#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16
	-#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT)
	-#define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31
	-#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0
	-#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT)
	-#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16
	-#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT)
	-#define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0
	-#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT)
	-#define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0
	-#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT)
	-#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPDINV_MAX_INDEX 31
	-#define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0
	-#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT)
	-#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT 15
	-#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT)
	-#define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16
	-#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT)
	-#define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT)
	-#define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0
	-#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT)
	-#define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0
	-#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT)
	-#define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0
	-#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT)
	-#define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0
	-#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT)
	-#define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT)
	-#define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT)
	-#define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0
	-#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT)
	-#define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT)
	-#define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0
	-#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT)
	-#define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0
	-#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT)
	-#define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0
	-#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT)
	-#define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
	-#define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT)
	-#define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0
	-#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT)
	-#define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0
	-#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT)
	-#define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0
	-#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT)
	-#define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0
	-#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT)
	-#define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0
	-#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT)
	-#define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT)
	-#define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0
	-#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT)
	-#define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31
	-#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
	-#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT)
	-#define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLHMC_VFSDPART_MAX_INDEX 31
	-#define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0
	-#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT)
	-#define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16
	-#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT)
	-#define I40E_GLPBLOC_CACHESIZE 0x000A80BC /* Reset: CORER */
	-#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT 0
	-#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT)
	-#define I40E_GLPBLOC_CACHESIZE_SETS_SHIFT 8
	-#define I40E_GLPBLOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPBLOC_CACHESIZE_SETS_SHIFT)
	-#define I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT 20
	-#define I40E_GLPBLOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT)
	-#define I40E_GLPDOC_CACHESIZE 0x000D0088 /* Reset: CORER */
	-#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT 0
	-#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT)
	-#define I40E_GLPDOC_CACHESIZE_SETS_SHIFT 8
	-#define I40E_GLPDOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPDOC_CACHESIZE_SETS_SHIFT)
	-#define I40E_GLPDOC_CACHESIZE_WAYS_SHIFT 20
	-#define I40E_GLPDOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPDOC_CACHESIZE_WAYS_SHIFT)
	-#define I40E_GLPEOC_CACHESIZE 0x000A60E8 /* Reset: CORER */
	-#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT 0
	-#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT)
	-#define I40E_GLPEOC_CACHESIZE_SETS_SHIFT 8
	-#define I40E_GLPEOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPEOC_CACHESIZE_SETS_SHIFT)
	-#define I40E_GLPEOC_CACHESIZE_WAYS_SHIFT 20
	-#define I40E_GLPEOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPEOC_CACHESIZE_WAYS_SHIFT)
	-#define I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT 15
	-#define I40E_PFHMC_PDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT)
	-#define I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT 15
	-#define I40E_PFHMC_SDCMD_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT)
	-#define I40E_GL_PPRS_SPARE 0x000856E0 /* Reset: CORER */
	-#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT 0
	-#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT)
	-#define I40E_GL_TLAN_SPARE 0x000E64E0 /* Reset: CORER */
	-#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT 0
	-#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT)
	-#define I40E_GL_TUPM_SPARE 0x000a2230 /* Reset: CORER */
	-#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT 0
	-#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG 0x000B81C0 /* Reset: POR */
	-#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT 0
	-#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT 1
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT 2
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT 3
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT 4
	-#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT 5
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT 6
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT 7
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT 8
	-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT 9
	-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT 10
	-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT 11
	-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT 12
	-#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT 13
	-#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT)
	-#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT 14
	-#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT)
	-#define I40E_GLGEN_MISC_SPARE 0x000880E0 /* Reset: POR */
	-#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT 0
	-#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT)
	-#define I40E_GL_UFUSE_SOC 0x000BE550 /* Reset: POR */
	-#define I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT 0
	-#define I40E_GL_UFUSE_SOC_PORT_MODE_MASK I40E_MASK(0x3, I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT)
	-#define I40E_GL_UFUSE_SOC_NIC_ID_SHIFT 2
	-#define I40E_GL_UFUSE_SOC_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_SOC_NIC_ID_SHIFT)
	-#define I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT 3
	-#define I40E_GL_UFUSE_SOC_SPARE_FUSES_MASK I40E_MASK(0x1FFF, I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT)
	-#define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30
	-#define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
	-#define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30
	-#define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
	-#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30
	-#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
	-#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30
	-#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
	-#define I40E_VPLAN_QBASE(_VF) (0x00074800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VPLAN_QBASE_MAX_INDEX 127
	-#define I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT 0
	-#define I40E_VPLAN_QBASE_VFFIRSTQ_MASK I40E_MASK(0x7FF, I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT)
	-#define I40E_VPLAN_QBASE_VFNUMQ_SHIFT 11
	-#define I40E_VPLAN_QBASE_VFNUMQ_MASK I40E_MASK(0xFF, I40E_VPLAN_QBASE_VFNUMQ_SHIFT)
	-#define I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT 31
	-#define I40E_VPLAN_QBASE_VFQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT)
	-#define I40E_PRTMAC_LINK_DOWN_COUNTER 0x001E2440 /* Reset: GLOBR */
	-#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT 0
	-#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT)
	-#define I40E_GLNVM_AL_REQ 0x000B6164 /* Reset: POR */
	-#define I40E_GLNVM_AL_REQ_POR_SHIFT 0
	-#define I40E_GLNVM_AL_REQ_POR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_POR_SHIFT)
	-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT 1
	-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT)
	-#define I40E_GLNVM_AL_REQ_GLOBR_SHIFT 2
	-#define I40E_GLNVM_AL_REQ_GLOBR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_GLOBR_SHIFT)
	-#define I40E_GLNVM_AL_REQ_CORER_SHIFT 3
	-#define I40E_GLNVM_AL_REQ_CORER_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_CORER_SHIFT)
	-#define I40E_GLNVM_AL_REQ_PE_SHIFT 4
	-#define I40E_GLNVM_AL_REQ_PE_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PE_SHIFT)
	-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT 5
	-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT)
	-#define I40E_GLNVM_ALTIMERS 0x000B6140 /* Reset: POR */
	-#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT 0
	-#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK I40E_MASK(0xFFF, I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT)
	-#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT 12
	-#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK I40E_MASK(0xFFFFF, I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT)
	-#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
	-#define I40E_GLNVM_FLA_LOCKED_SHIFT 6
	-#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
	-
	-#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
	-#define I40E_GLNVM_ULD_PCIER_DONE_SHIFT 0
	-#define I40E_GLNVM_ULD_PCIER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_SHIFT)
	-#define I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT 1
	-#define I40E_GLNVM_ULD_PCIER_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT)
	-#define I40E_GLNVM_ULD_CORER_DONE_SHIFT 3
	-#define I40E_GLNVM_ULD_CORER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CORER_DONE_SHIFT)
	-#define I40E_GLNVM_ULD_GLOBR_DONE_SHIFT 4
	-#define I40E_GLNVM_ULD_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_GLOBR_DONE_SHIFT)
	-#define I40E_GLNVM_ULD_POR_DONE_SHIFT 5
	-#define I40E_GLNVM_ULD_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_SHIFT)
	-#define I40E_GLNVM_ULD_POR_DONE_1_SHIFT 8
	-#define I40E_GLNVM_ULD_POR_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_1_SHIFT)
	-#define I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT 9
	-#define I40E_GLNVM_ULD_PCIER_DONE_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT)
	-#define I40E_GLNVM_ULD_PE_DONE_SHIFT 10
	-#define I40E_GLNVM_ULD_PE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PE_DONE_SHIFT)
	-#define I40E_GLNVM_ULT 0x000B6154 /* Reset: POR */
	-#define I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT 0
	-#define I40E_GLNVM_ULT_CONF_PCIR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT)
	-#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT 1
	-#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT)
	-#define I40E_GLNVM_ULT_RESERVED_1_SHIFT 2
	-#define I40E_GLNVM_ULT_RESERVED_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_1_SHIFT)
	-#define I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT 3
	-#define I40E_GLNVM_ULT_CONF_CORE_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT)
	-#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT 4
	-#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT)
	-#define I40E_GLNVM_ULT_CONF_POR_AE_SHIFT 5
	-#define I40E_GLNVM_ULT_CONF_POR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_POR_AE_SHIFT)
	-#define I40E_GLNVM_ULT_RESERVED_2_SHIFT 6
	-#define I40E_GLNVM_ULT_RESERVED_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_2_SHIFT)
	-#define I40E_GLNVM_ULT_RESERVED_3_SHIFT 7
	-#define I40E_GLNVM_ULT_RESERVED_3_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_3_SHIFT)
	-#define I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT 8
	-#define I40E_GLNVM_ULT_CONF_EMP_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT)
	-#define I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT 9
	-#define I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT)
	-#define I40E_GLNVM_ULT_RESERVED_4_SHIFT 10
	-#define I40E_GLNVM_ULT_RESERVED_4_MASK I40E_MASK(0x3FFFFF, I40E_GLNVM_ULT_RESERVED_4_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT 0x000B615C /* Reset: POR */
	-#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT 0
	-#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT 1
	-#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT 2
	-#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT 3
	-#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT 4
	-#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT 5
	-#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT 6
	-#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT 7
	-#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT 8
	-#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT 9
	-#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT 10
	-#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT 11
	-#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT 12
	-#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT 13
	-#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT 14
	-#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT 15
	-#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT)
	-#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT 16
	-#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT)
	-#define I40E_MNGSB_DADD 0x000B7030 /* Reset: POR */
	-#define I40E_MNGSB_DADD_ADDR_SHIFT 0
	-#define I40E_MNGSB_DADD_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DADD_ADDR_SHIFT)
	-#define I40E_MNGSB_DCNT 0x000B7034 /* Reset: POR */
	-#define I40E_MNGSB_DCNT_BYTE_CNT_SHIFT 0
	-#define I40E_MNGSB_DCNT_BYTE_CNT_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DCNT_BYTE_CNT_SHIFT)
	-#define I40E_MNGSB_MSGCTL 0x000B7020 /* Reset: POR */
	-#define I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT 0
	-#define I40E_MNGSB_MSGCTL_HDR_DWS_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT)
	-#define I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT 8
	-#define I40E_MNGSB_MSGCTL_EXP_RDW_MASK I40E_MASK(0x1FF, I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT)
	-#define I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT 26
	-#define I40E_MNGSB_MSGCTL_MSG_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT)
	-#define I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT 28
	-#define I40E_MNGSB_MSGCTL_TOKEN_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT)
	-#define I40E_MNGSB_MSGCTL_BARCLR_SHIFT 30
	-#define I40E_MNGSB_MSGCTL_BARCLR_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_BARCLR_SHIFT)
	-#define I40E_MNGSB_MSGCTL_CMDV_SHIFT 31
	-#define I40E_MNGSB_MSGCTL_CMDV_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_CMDV_SHIFT)
	-#define I40E_MNGSB_RDATA 0x000B7300 /* Reset: POR */
	-#define I40E_MNGSB_RDATA_DATA_SHIFT 0
	-#define I40E_MNGSB_RDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_RDATA_DATA_SHIFT)
	-#define I40E_MNGSB_RHDR0 0x000B72FC /* Reset: POR */
	-#define I40E_MNGSB_RHDR0_DESTINATION_SHIFT 0
	-#define I40E_MNGSB_RHDR0_DESTINATION_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_DESTINATION_SHIFT)
	-#define I40E_MNGSB_RHDR0_SOURCE_SHIFT 8
	-#define I40E_MNGSB_RHDR0_SOURCE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_SOURCE_SHIFT)
	-#define I40E_MNGSB_RHDR0_OPCODE_SHIFT 16
	-#define I40E_MNGSB_RHDR0_OPCODE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_OPCODE_SHIFT)
	-#define I40E_MNGSB_RHDR0_TAG_SHIFT 24
	-#define I40E_MNGSB_RHDR0_TAG_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_TAG_SHIFT)
	-#define I40E_MNGSB_RHDR0_RESPONSE_SHIFT 27
	-#define I40E_MNGSB_RHDR0_RESPONSE_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_RESPONSE_SHIFT)
	-#define I40E_MNGSB_RHDR0_EH_SHIFT 31
	-#define I40E_MNGSB_RHDR0_EH_MASK I40E_MASK(0x1, I40E_MNGSB_RHDR0_EH_SHIFT)
	-#define I40E_MNGSB_RSPCTL 0x000B7024 /* Reset: POR */
	-#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT 0
	-#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_MASK I40E_MASK(0x1FF, I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT)
	-#define I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT 26
	-#define I40E_MNGSB_RSPCTL_RSP_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT)
	-#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT 30
	-#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT)
	-#define I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT 31
	-#define I40E_MNGSB_RSPCTL_RSP_ERR_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT)
	-#define I40E_MNGSB_WDATA 0x000B7100 /* Reset: POR */
	-#define I40E_MNGSB_WDATA_DATA_SHIFT 0
	-#define I40E_MNGSB_WDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WDATA_DATA_SHIFT)
	-#define I40E_MNGSB_WHDR0 0x000B70F4 /* Reset: POR */
	-#define I40E_MNGSB_WHDR0_RAW_DEST_SHIFT 0
	-#define I40E_MNGSB_WHDR0_RAW_DEST_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_RAW_DEST_SHIFT)
	-#define I40E_MNGSB_WHDR0_DEST_SEL_SHIFT 12
	-#define I40E_MNGSB_WHDR0_DEST_SEL_MASK I40E_MASK(0xF, I40E_MNGSB_WHDR0_DEST_SEL_SHIFT)
	-#define I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT 16
	-#define I40E_MNGSB_WHDR0_OPCODE_SEL_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT)
	-#define I40E_MNGSB_WHDR0_TAG_SHIFT 24
	-#define I40E_MNGSB_WHDR0_TAG_MASK I40E_MASK(0x7F, I40E_MNGSB_WHDR0_TAG_SHIFT)
	-#define I40E_MNGSB_WHDR1 0x000B70F8 /* Reset: POR */
	-#define I40E_MNGSB_WHDR1_ADDR_SHIFT 0
	-#define I40E_MNGSB_WHDR1_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR1_ADDR_SHIFT)
	-#define I40E_MNGSB_WHDR2 0x000B70FC /* Reset: POR */
	-#define I40E_MNGSB_WHDR2_LENGTH_SHIFT 0
	-#define I40E_MNGSB_WHDR2_LENGTH_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR2_LENGTH_SHIFT)
	-
	-#define I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT 21
	-#define I40E_GLPCI_CAPSUP_WAKUP_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT)
	-
	-#define I40E_GLPCI_CUR_CLNT_COMMON 0x0009CA18 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_CLNT_PIPEMON 0x0009CA20 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_MNG_ALWD 0x0009c514 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_MNG_RSVD 0x0009c594 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_PMAT_ALWD 0x0009c510 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_PMAT_RSVD 0x0009c590 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_RLAN_ALWD 0x0009c500 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_RLAN_RSVD 0x0009c580 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_RXPE_ALWD 0x0009c508 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_RXPE_RSVD 0x0009c588 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_TDPU_ALWD 0x0009c518 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_TDPU_RSVD 0x0009c598 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_TLAN_ALWD 0x0009c504 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_TLAN_RSVD 0x0009c584 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_TXPE_ALWD 0x0009c50C /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_TXPE_RSVD 0x0009c58c /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT)
	-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON 0x0009CA28 /* Reset: PCIR */
	-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT 16
	-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT)
	-
	-#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4
	-#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT)
	-#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10
	-#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT)
	-#define I40E_GLPCI_NPQ_CFG 0x0009CA00 /* Reset: PCIR */
	-#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT 0
	-#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT)
	-#define I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT 1
	-#define I40E_GLPCI_NPQ_CFG_SMALL_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT)
	-#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT 2
	-#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT)
	-#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT 6
	-#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_MASK I40E_MASK(0x3FF, I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT)
	-#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT 16
	-#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT)
	-#define I40E_GLPCI_WATMK_CLNT_PIPEMON 0x0009CA30 /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_MNG_ALWD 0x0009CB14 /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_WATMK_PMAT_ALWD 0x0009CB10 /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_WATMK_RLAN_ALWD 0x0009CB00 /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_WATMK_RXPE_ALWD 0x0009CB08 /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_WATMK_TLAN_ALWD 0x0009CB04 /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_WATMK_TPDU_ALWD 0x0009CB18 /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT)
	-#define I40E_GLPCI_WATMK_TXPE_ALWD 0x0009CB0c /* Reset: PCIR */
	-#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT 0
	-#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT)
	-#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT 16
	-#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT)
	-#define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */
	-#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0
	-#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
	-#define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */
	-#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0
	-#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT)
	-#define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */
	-#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0
	-#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT)
	-#define I40E_GLPE_CPUTRIG0 0x0000D060 /* Reset: PE_CORER */
	-#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT 0
	-#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK I40E_MASK(0xFFFF, I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT)
	-#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT 17
	-#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT)
	-#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT 18
	-#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT)
	-#define I40E_GLPE_DUAL40_RUPM 0x0000DA04 /* Reset: PE_CORER */
	-#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT 0
	-#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK I40E_MASK(0x1, I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT)
	-#define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLPE_PFAEQEDROPCNT_MAX_INDEX 15
	-#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0
	-#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
	-#define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLPE_PFCEQEDROPCNT_MAX_INDEX 15
	-#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0
	-#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
	-#define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	-#define I40E_GLPE_PFCQEDROPCNT_MAX_INDEX 15
	-#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT 0
	-#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT)
	-#define I40E_GLPE_RUPM_CQPPOOL 0x0000DACC /* Reset: PE_CORER */
	-#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT 0
	-#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT)
	-#define I40E_GLPE_RUPM_FLRPOOL 0x0000DAC4 /* Reset: PE_CORER */
	-#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT 0
	-#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT)
	-#define I40E_GLPE_RUPM_GCTL 0x0000DA00 /* Reset: PE_CORER */
	-#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT 0
	-#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT)
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT 26
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT)
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT 27
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT)
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT 28
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT)
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT 29
	-#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT)
	-#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT 30
	-#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT)
	-#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT 31
	-#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT)
	-#define I40E_GLPE_RUPM_PTXPOOL 0x0000DAC8 /* Reset: PE_CORER */
	-#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT 0
	-#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT)
	-#define I40E_GLPE_RUPM_PUSHPOOL 0x0000DAC0 /* Reset: PE_CORER */
	-#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT 0
	-#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT)
	-#define I40E_GLPE_RUPM_TXHOST_EN 0x0000DA08 /* Reset: PE_CORER */
	-#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT 0
	-#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT)
	-#define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLPE_VFAEQEDROPCNT_MAX_INDEX 31
	-#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0
	-#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
	-#define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLPE_VFCEQEDROPCNT_MAX_INDEX 31
	-#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0
	-#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
	-#define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	-#define I40E_GLPE_VFCQEDROPCNT_MAX_INDEX 31
	-#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT 0
	-#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT)
	-#define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31
	-#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
	-#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
	-#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
	-#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
	-#define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
	-#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
	-#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
	-#define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
	-#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
	-#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT)
	-#define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPE_VFUDACTRL_MAX_INDEX 31
	-#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0
	-#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT)
	-#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1
	-#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT)
	-#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2
	-#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT)
	-#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3
	-#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT)
	-#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
	-#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT)
	-#define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31
	-#define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0
	-#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT)
	-#define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31
	-#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT)
	-#define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
	-#define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0
	-#define I40E_PFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_AEQALLOC_AECOUNT_SHIFT)
	-#define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
	-#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
	-#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
	-#define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
	-#define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0
	-#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT)
	-#define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */
	-#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
	-#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
	-#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4
	-#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
	-#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16
	-#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
	-#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
	-#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
	-#define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */
	-#define I40E_PFPE_CQACK_PECQID_SHIFT 0
	-#define I40E_PFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQACK_PECQID_SHIFT)
	-#define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */
	-#define I40E_PFPE_CQARM_PECQID_SHIFT 0
	-#define I40E_PFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQARM_PECQID_SHIFT)
	-#define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */
	-#define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0
	-#define I40E_PFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPDB_WQHEAD_SHIFT)
	-#define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */
	-#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
	-#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
	-#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
	-#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
	-#define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */
	-#define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0
	-#define I40E_PFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
	-#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
	-#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
	-#define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 /* Reset: PFR */
	-#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
	-#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
	-#define I40E_PFPE_FLMXMITALLOCERR 0x00008900 /* Reset: PFR */
	-#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
	-#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT)
	-#define I40E_PFPE_IPCONFIG0 0x00008280 /* Reset: PFR */
	-#define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0
	-#define I40E_PFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
	-#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
	-#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
	-#define I40E_PFPE_MRTEIDXMASK 0x00008600 /* Reset: PFR */
	-#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
	-#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
	-#define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 /* Reset: PFR */
	-#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
	-#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
	-#define I40E_PFPE_TCPNOWTIMER 0x00008580 /* Reset: PFR */
	-#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
	-#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
	-#define I40E_PFPE_UDACTRL 0x00008700 /* Reset: PFR */
	-#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0
	-#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT)
	-#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1
	-#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT)
	-#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2
	-#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT)
	-#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3
	-#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT)
	-#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
	-#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT)
	-#define I40E_PFPE_UDAUCFBQPN 0x00008780 /* Reset: PFR */
	-#define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0
	-#define I40E_PFPE_UDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_PFPE_UDAUCFBQPN_QPN_SHIFT)
	-#define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31
	-#define I40E_PFPE_UDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_PFPE_UDAUCFBQPN_VALID_SHIFT)
	-#define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */
	-#define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0
	-#define I40E_PFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_PFPE_WQEALLOC_PEQPID_SHIFT)
	-#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
	-#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
	-#define I40E_PRTDCB_RLPMC 0x0001F140 /* Reset: PE_CORER */
	-#define I40E_PRTDCB_RLPMC_TC2PFC_SHIFT 0
	-#define I40E_PRTDCB_RLPMC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RLPMC_TC2PFC_SHIFT)
	-#define I40E_PRTDCB_TCMSTC_RLPM(_i) (0x0001F040 + ((_i) * 32)) /* _i=0...7 / / Reset: PE_CORER */
	-#define I40E_PRTDCB_TCMSTC_RLPM_MAX_INDEX 7
	-#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT 0
	-#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT)
	-#define I40E_PRTDCB_TCPMC_RLPM 0x0001F1A0 /* Reset: PE_CORER */
	-#define I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT 0
	-#define I40E_PRTDCB_TCPMC_RLPM_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT)
	-#define I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT 13
	-#define I40E_PRTDCB_TCPMC_RLPM_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT)
	-#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT 30
	-#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT)
	-#define I40E_PRTE_RUPM_TCCNTR03 0x0000DAE0 /* Reset: PE_CORER */
	-#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT 0
	-#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT)
	-#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT 8
	-#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT)
	-#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT 16
	-#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT)
	-#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT 24
	-#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_CNTR 0x0000DB20 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT 0
	-#define I40E_PRTPE_RUPM_CNTR_COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_CTL 0x0000DA40 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_CTL_LLTC_SHIFT 13
	-#define I40E_PRTPE_RUPM_CTL_LLTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CTL_LLTC_SHIFT)
	-#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT 30
	-#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT)
	-#define I40E_PRTPE_RUPM_PFCCTL 0x0000DA60 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT 0
	-#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT)
	-#define I40E_PRTPE_RUPM_PFCPC 0x0000DA80 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT 0
	-#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT)
	-#define I40E_PRTPE_RUPM_PFCTCC 0x0000DAA0 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT 0
	-#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT)
	-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT 16
	-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT)
	-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT 31
	-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT)
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47 0x0000DB60 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT 0
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT 8
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT 16
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT 24
	-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03 0x0000DB40 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT 0
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT 8
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT 16
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT 24
	-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_TCCNTR47 0x0000DB00 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT 0
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT 8
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT 16
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT 24
	-#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT)
	-#define I40E_PRTPE_RUPM_THRES 0x0000DA20 /* Reset: PE_CORER */
	-#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT 0
	-#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT)
	-#define I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT 8
	-#define I40E_PRTPE_RUPM_THRES_MAXSPADS_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT)
	-#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT 16
	-#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT)
	-#define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_AEQALLOC_MAX_INDEX 127
	-#define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0
	-#define I40E_VFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC_AECOUNT_SHIFT)
	-#define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CCQPHIGH_MAX_INDEX 127
	-#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
	-#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
	-#define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CCQPLOW_MAX_INDEX 127
	-#define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0
	-#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127
	-#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
	-#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4
	-#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16
	-#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
	-#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
	-#define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CQACK_MAX_INDEX 127
	-#define I40E_VFPE_CQACK_PECQID_SHIFT 0
	-#define I40E_VFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK_PECQID_SHIFT)
	-#define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CQARM_MAX_INDEX 127
	-#define I40E_VFPE_CQARM_PECQID_SHIFT 0
	-#define I40E_VFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM_PECQID_SHIFT)
	-#define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CQPDB_MAX_INDEX 127
	-#define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0
	-#define I40E_VFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB_WQHEAD_SHIFT)
	-#define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CQPERRCODES_MAX_INDEX 127
	-#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
	-#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
	-#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
	-#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
	-#define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_CQPTAIL_MAX_INDEX 127
	-#define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0
	-#define I40E_VFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL_WQTAIL_SHIFT)
	-#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
	-#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
	-#define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_IPCONFIG0_MAX_INDEX 127
	-#define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0
	-#define I40E_VFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
	-#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
	-#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
	-#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127
	-#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
	-#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
	-#define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127
	-#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
	-#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
	-#define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127
	-#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
	-#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
	-#define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	-#define I40E_VFPE_WQEALLOC_MAX_INDEX 127
	-#define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0
	-#define I40E_VFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC_PEQPID_SHIFT)
	-#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
	-#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
	-#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
	-#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
	-#define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
	-#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
	-#define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
	-#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
	-#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
	-#define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
	-#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
	-#define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
	-#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
	-#define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
	-#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
	-#define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
	-#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
	-#define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
	-#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
	-#define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
	-#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
	-#define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
	-#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
	-#define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
	-#define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
	-#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
	-#define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
	-#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
	-#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
	-#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
	-#define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
	-#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
	-#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
	-#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
	-#define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
	-#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
	-#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
	-#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
	-#define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
	-#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
	-#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
	-#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
	-#define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
	-#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
	-#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
	-#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
	-#define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
	-#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
	-#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
	-#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
	-#define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
	-#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
	-#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
	-#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
	-#define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0
	-#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT)
	-#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15
	-#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0
	-#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT)
	-#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15
	-#define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0
	-#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT)
	-#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15
	-#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0
	-#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT)
	-#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15
	-#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
	-#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
	-#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15
	-#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
	-#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
	-#define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
	-#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
	-#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
	-#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
	-#define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15
	-#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
	-#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
	-#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15
	-#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
	-#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
	-#define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
	-#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
	-#define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15
	-#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
	-#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
	-#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	-#define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15
	-#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
	-#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
	-#define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 /* Reset: PE_CORER */
	-#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0
	-#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT)
	-#define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 /* Reset: PE_CORER */
	-#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0
	-#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT)
	-#define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C /* Reset: PE_CORER */
	-#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0
	-#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT)
	-#define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 /* Reset: PE_CORER */
	-#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0
	-#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT)
	-#define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 /* Reset: PE_CORER */
	-#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0
	-#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT)
	-#define I40E_GLPES_RDMARXUNALIGN 0x0001E000 /* Reset: PE_CORER */
	-#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0
	-#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT)
	-#define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0
	-#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT)
	-#define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0
	-#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT)
	-#define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0
	-#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT)
	-#define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0
	-#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT)
	-#define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0
	-#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT)
	-#define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0
	-#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT)
	-#define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0
	-#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT)
	-#define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0
	-#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT)
	-#define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0
	-#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT)
	-#define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0
	-#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT)
	-#define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0
	-#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT)
	-#define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0
	-#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT)
	-#define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0
	-#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT)
	-#define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0
	-#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT)
	-#define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0
	-#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT)
	-#define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 /* Reset: PE_CORER */
	-#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0
	-#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
	-#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
	-#define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
	-#define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
	-#define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
	-#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
	-#define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
	-#define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
	-#define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
	-#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
	-#define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
	-#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
	-#define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
	-#define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
	-#define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
	-#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
	-#define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
	-#define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
	-#define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
	-#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
	-#define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
	-#define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
	-#define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
	-#define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
	-#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
	-#define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
	-#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
	-#define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
	-#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
	-#define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
	-#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
	-#define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
	-#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
	-#define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
	-#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
	-#define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
	-#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
	-#define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
	-#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
	-#define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
	-#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
	-#define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
	-#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
	-#define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
	-#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
	-#define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
	-#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
	-#define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
	-#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
	-#define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
	-#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
	-#define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0
	-#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT)
	-#define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31
	-#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0
	-#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT)
	-#define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31
	-#define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0
	-#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT)
	-#define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31
	-#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0
	-#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT)
	-#define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31
	-#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
	-#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
	-#define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31
	-#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
	-#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
	-#define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
	-#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
	-#define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
	-#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
	-#define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31
	-#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
	-#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
	-#define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31
	-#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
	-#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
	-#define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
	-#define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
	-#define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31
	-#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
	-#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
	-#define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	-#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31
	-#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
	-#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
	-#define I40E_GLGEN_PME_TO 0x000B81BC /* Reset: POR */
	-#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT 0
	-#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_MASK I40E_MASK(0x1, I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT)
	-#define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 / / Reset: CORER */
	-#define I40E_GLQF_APBVT_MAX_INDEX 2047
	-#define I40E_GLQF_APBVT_APBVT_SHIFT 0
	-#define I40E_GLQF_APBVT_APBVT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_APBVT_APBVT_SHIFT)
	-#define I40E_GLQF_FD_PCTYPES(_i) (0x00268000 + ((_i) * 4)) /* _i=0...63 / / Reset: POR */
	-#define I40E_GLQF_FD_PCTYPES_MAX_INDEX 63
	-#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT 0
	-#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT)
	-#define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 / / Reset: CORER */
	-#define I40E_GLQF_FDEVICTENA_MAX_INDEX 1
	-#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT 0
	-#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT)
	-#define I40E_GLQF_FDEVICTFLAG 0x00270280 /* Reset: CORER */
	-#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT 0
	-#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT)
	-#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT 8
	-#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT)
	-#define I40E_PFQF_CTL_2 0x00270300 /* Reset: CORER */
	-#define I40E_PFQF_CTL_2_PEHSIZE_SHIFT 0
	-#define I40E_PFQF_CTL_2_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEHSIZE_SHIFT)
	-#define I40E_PFQF_CTL_2_PEDSIZE_SHIFT 5
	-#define I40E_PFQF_CTL_2_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEDSIZE_SHIFT)
	-/* Redefined for X722 family */
	-#define I40E_X722_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 / / Reset: CORER */
	-#define I40E_X722_PFQF_HLUT_MAX_INDEX 127
	-#define I40E_X722_PFQF_HLUT_LUT0_SHIFT 0
	-#define I40E_X722_PFQF_HLUT_LUT0_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT0_SHIFT)
	-#define I40E_X722_PFQF_HLUT_LUT1_SHIFT 8
	-#define I40E_X722_PFQF_HLUT_LUT1_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT1_SHIFT)
	-#define I40E_X722_PFQF_HLUT_LUT2_SHIFT 16
	-#define I40E_X722_PFQF_HLUT_LUT2_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT2_SHIFT)
	-#define I40E_X722_PFQF_HLUT_LUT3_SHIFT 24
	-#define I40E_X722_PFQF_HLUT_LUT3_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT3_SHIFT)
	-#define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 / / Reset: CORER */
	-#define I40E_PFQF_HREGION_MAX_INDEX 7
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_0_SHIFT 1
	-#define I40E_PFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT)
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_1_SHIFT 5
	-#define I40E_PFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT)
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_2_SHIFT 9
	-#define I40E_PFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT)
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_3_SHIFT 13
	-#define I40E_PFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT)
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_4_SHIFT 17
	-#define I40E_PFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT)
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_5_SHIFT 21
	-#define I40E_PFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT)
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_6_SHIFT 25
	-#define I40E_PFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT)
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
	-#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
	-#define I40E_PFQF_HREGION_REGION_7_SHIFT 29
	-#define I40E_PFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT)
	-#define I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT 8
	-#define I40E_VSIQF_CTL_RSS_LUT_TYPE_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT)
	-#define I40E_VSIQF_HKEY(_i, _VSI) (0x002A0000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...12, _VSI=0...383 / / Reset: CORER */
	-#define I40E_VSIQF_HKEY_MAX_INDEX 12
	-#define I40E_VSIQF_HKEY_KEY_0_SHIFT 0
	-#define I40E_VSIQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_0_SHIFT)
	-#define I40E_VSIQF_HKEY_KEY_1_SHIFT 8
	-#define I40E_VSIQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_1_SHIFT)
	-#define I40E_VSIQF_HKEY_KEY_2_SHIFT 16
	-#define I40E_VSIQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_2_SHIFT)
	-#define I40E_VSIQF_HKEY_KEY_3_SHIFT 24
	-#define I40E_VSIQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_3_SHIFT)
	-#define I40E_VSIQF_HLUT(_i, _VSI) (0x00220000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...15, _VSI=0...383 / / Reset: CORER */
	-#define I40E_VSIQF_HLUT_MAX_INDEX 15
	-#define I40E_VSIQF_HLUT_LUT0_SHIFT 0
	-#define I40E_VSIQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT0_SHIFT)
	-#define I40E_VSIQF_HLUT_LUT1_SHIFT 8
	-#define I40E_VSIQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT1_SHIFT)
	-#define I40E_VSIQF_HLUT_LUT2_SHIFT 16
	-#define I40E_VSIQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT2_SHIFT)
	-#define I40E_VSIQF_HLUT_LUT3_SHIFT 24
	-#define I40E_VSIQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT3_SHIFT)
	-#define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */
	-#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT 0
	-#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT)
	-#define I40E_GLGEN_STAT_HALT 0x00390000 /* Reset: CORER */
	-#define I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT 0
	-#define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT)
	-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30
	-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
	-#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
	-#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
	-#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
	-#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
	-#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
	-#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
	-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
	-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
	-#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
	-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
	-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
	-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
	-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4
	-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16
	-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
	-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
	-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
	-#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
	-#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
	-#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)
	-#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
	-#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
	-#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)
	-#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
	-#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
	-#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
	-#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
	-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
	-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
	-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
	-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
	-#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
	-#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
	-#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
	-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
	-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
	-#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */
	-#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
	-#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
	-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
	-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
	-#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */
	-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
	-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
	-#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */
	-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
	-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
	-#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */
	-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
	-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
	-#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
	-#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
	-#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
	-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
	-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
	-
	-#endif /* X722_SUPPORT */
	#endif /* _I40E_REGISTER_H_ */
	Index: head/sys/dev/ixl/i40e_status.h
	===================================================================
	--- head/sys/dev/ixl/i40e_status.h
	+++ head/sys/dev/ixl/i40e_status.h
	@@ -1,6 +1,6 @@
	/******************************************************************************

	- Copyright (c) 2013-2014, Intel Corporation
	+ Copyright (c) 2013-2015, Intel Corporation
	All rights reserved.

	Redistribution and use in source and binary forms, with or without
	Index: head/sys/dev/ixl/i40e_type.h
	===================================================================
	--- head/sys/dev/ixl/i40e_type.h
	+++ head/sys/dev/ixl/i40e_type.h
	@@ -174,10 +174,6 @@
	I40E_MAC_X710,
	I40E_MAC_XL710,
	I40E_MAC_VF,
	-#ifdef X722_SUPPORT
	- I40E_MAC_X722,
	- I40E_MAC_X722_VF,
	-#endif
	I40E_MAC_GENERIC,
	};

	@@ -297,7 +293,7 @@
	bool get_link_info;
	enum i40e_media_type media_type;
	/* all the phy types the NVM is capable of */
	- enum i40e_aq_capabilities_phy_type phy_types;
	+ u32 phy_types;
	};

	#define I40E_HW_CAP_MAX_GPIO 30
	@@ -550,6 +546,8 @@
	u8 dcbx_mode;
	#define I40E_DCBX_MODE_CEE 0x1
	#define I40E_DCBX_MODE_IEEE 0x2
	+ u8 app_mode;
	+#define I40E_DCBX_APPS_NON_WILLING 0x1
	u32 numapps;
	u32 tlv_status; /* CEE mode TLV status */
	struct i40e_dcb_ets_config etscfg;
	@@ -624,12 +622,7 @@

	static INLINE bool i40e_is_vf(struct i40e_hw *hw)
	{
	-#ifdef X722_SUPPORT
	- return (hw->mac.type == I40E_MAC_VF \|\|
	- hw->mac.type == I40E_MAC_X722_VF);
	-#else
	return hw->mac.type == I40E_MAC_VF;
	-#endif
	}

	struct i40e_driver_version {
	@@ -733,11 +726,7 @@
	I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
	I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
	I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
	-#ifdef X722_SUPPORT
	- I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
	-#else
	I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
	-#endif

	I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
	I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
	@@ -745,11 +734,7 @@
	I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
	I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
	I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
	-#ifdef X722_SUPPORT
	- I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
	-#else
	I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
	-#endif
	I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
	};

	@@ -1127,10 +1112,6 @@
	#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
	I40E_TXD_CTX_QW0_DECTTL_SHIFT)

	-#ifdef X722_SUPPORT
	-#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
	-#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
	-#endif
	struct i40e_nop_desc {
	__le64 rsvd;
	__le64 dtype_cmd;
	@@ -1167,38 +1148,15 @@

	/* Packet Classifier Types for filters */
	enum i40e_filter_pctype {
	-#ifdef X722_SUPPORT
	- /* Note: Values 0-28 are reserved for future use.
	- * Value 29, 30, 32 are not supported on XL710 and X710.
	- */
	- I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
	- I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
	-#else
	/* Note: Values 0-30 are reserved for future use */
	-#endif
	I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
	-#ifdef X722_SUPPORT
	- I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
	-#else
	/* Note: Value 32 is reserved for future use */
	-#endif
	I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
	I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
	I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
	I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
	-#ifdef X722_SUPPORT
	- /* Note: Values 37-38 are reserved for future use.
	- * Value 39, 40, 42 are not supported on XL710 and X710.
	- */
	- I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
	- I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
	-#else
	/* Note: Values 37-40 are reserved for future use */
	-#endif
	I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
	-#ifdef X722_SUPPORT
	- I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
	-#endif
	I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
	I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
	I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
	@@ -1252,12 +1210,6 @@
	I40E_TXD_FLTR_QW1_CMD_SHIFT)
	#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
	I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
	-#ifdef X722_SUPPORT
	-
	-#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
	- I40E_TXD_FLTR_QW1_CMD_SHIFT)
	-#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
	-#endif

	#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
	#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
	Index: head/sys/dev/ixl/i40e_virtchnl.h
	===================================================================
	--- head/sys/dev/ixl/i40e_virtchnl.h
	+++ head/sys/dev/ixl/i40e_virtchnl.h
	@@ -158,6 +158,7 @@
	#define I40E_VIRTCHNL_VF_OFFLOAD_FCOE 0x00000004
	#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ 0x00000008
	#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG 0x00000010
	+#define I40E_VIRTCHNL_VF_OFFLOAD_WB_ON_ITR 0x00000020
	#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000
	#define I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING 0x00020000

	Index: head/sys/dev/ixl/if_ixl.c
	===================================================================
	--- head/sys/dev/ixl/if_ixl.c
	+++ head/sys/dev/ixl/if_ixl.c
	@@ -48,7 +48,7 @@
	/*********************************************************************
	* Driver version
	*********************************************************************/
	-char ixl_driver_version[] = "1.4.3";
	+char ixl_driver_version[] = "1.4.5-k";

	/*********************************************************************
	* PCI Device ID Table
	@@ -63,6 +63,7 @@
	static ixl_vendor_info_t ixl_vendor_info_array[] =
	{
	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710, 0, 0, 0},
	+ {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_A, 0, 0, 0},
	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B, 0, 0, 0},
	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C, 0, 0, 0},
	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A, 0, 0, 0},
	@@ -70,11 +71,8 @@
	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C, 0, 0, 0},
	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T, 0, 0, 0},
	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4, 0, 0, 0},
	-#ifdef X722_SUPPORT
	- {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722, 0, 0, 0},
	- {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722, 0, 0, 0},
	- {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722, 0, 0, 0},
	-#endif
	+ {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2, 0, 0, 0},
	+ {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A, 0, 0, 0},
	/* required last entry */
	{0, 0, 0, 0, 0}
	};
	@@ -115,8 +113,6 @@
	static void ixl_configure_msix(struct ixl_pf *);
	static void ixl_configure_itr(struct ixl_pf *);
	static void ixl_configure_legacy(struct ixl_pf *);
	-static void ixl_init_taskqueues(struct ixl_pf *);
	-static void ixl_free_taskqueues(struct ixl_pf *);
	static void ixl_free_pci_resources(struct ixl_pf *);
	static void ixl_local_timer(void *);
	static int ixl_setup_interface(device_t, struct ixl_vsi *);
	@@ -159,10 +155,8 @@


	/* Sysctl debug interface */
	-#ifdef IXL_DEBUG_SYSCTL
	static int ixl_debug_info(SYSCTL_HANDLER_ARGS);
	static void ixl_print_debug_info(struct ixl_pf *);
	-#endif

	/* The MSI/X Interrupt handlers */
	static void ixl_intr(void *);
	@@ -207,8 +201,8 @@
	#ifdef PCI_IOV
	static int ixl_adminq_err_to_errno(enum i40e_admin_queue_err err);

	-static int ixl_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t*);
	-static void ixl_iov_uninit(device_t dev);
	+static int ixl_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t*);
	+static void ixl_uninit_iov(device_t dev);
	static int ixl_add_vf(device_t dev, uint16_t vfnum, const nvlist_t*);

	static void ixl_handle_vf_msg(struct ixl_pf *,
	@@ -230,9 +224,9 @@
	DEVMETHOD(device_detach, ixl_detach),
	DEVMETHOD(device_shutdown, ixl_shutdown),
	#ifdef PCI_IOV
	- DEVMETHOD(pci_iov_init, ixl_iov_init),
	- DEVMETHOD(pci_iov_uninit, ixl_iov_uninit),
	- DEVMETHOD(pci_iov_add_vf, ixl_add_vf),
	+ DEVMETHOD(pci_init_iov, ixl_init_iov),
	+ DEVMETHOD(pci_uninit_iov, ixl_uninit_iov),
	+ DEVMETHOD(pci_add_vf, ixl_add_vf),
	#endif
	{0, 0}
	};
	@@ -644,7 +638,7 @@
	else
	error = ixl_assign_vsi_legacy(pf);
	if (error)
	- goto err_mac_hmc;
	+ goto err_late;

	if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) \|\|
	(hw->aq.fw_maj_ver < 4)) {
	@@ -669,22 +663,19 @@
	error = ixl_switch_config(pf);
	if (error) {
	device_printf(dev, "Initial switch config failed: %d\n", error);
	- goto err_late;
	+ goto err_mac_hmc;
	}

	/* Limit phy interrupts to link and modules failure */
	- error = i40e_aq_set_phy_int_mask(hw, ~(I40E_AQ_EVENT_LINK_UPDOWN \|
	- I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
	- if (error)
	+ error = i40e_aq_set_phy_int_mask(hw,
	+ I40E_AQ_EVENT_LINK_UPDOWN \| I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
	+ if (error)
	device_printf(dev, "set phy mask failed: %d\n", error);

	/* Get the bus configuration and set the shared code */
	bus = ixl_get_bus_info(hw, dev);
	i40e_set_pci_config_data(hw, bus);

	- /* Initialize taskqueues */
	- ixl_init_taskqueues(pf);
	-
	/* Initialize statistics */
	ixl_pf_reset_stats(pf);
	ixl_update_stats_counters(pf);
	@@ -753,6 +744,7 @@
	struct ixl_pf *pf = device_get_softc(dev);
	struct i40e_hw *hw = &pf->hw;
	struct ixl_vsi *vsi = &pf->vsi;
	+ struct ixl_queue *que = vsi->queues;
	i40e_status status;
	#ifdef PCI_IOV
	int error;
	@@ -781,7 +773,13 @@
	IXL_PF_UNLOCK(pf);
	}

	- ixl_free_taskqueues(pf);
	+ for (int i = 0; i < vsi->num_queues; i++, que++) {
	+ if (que->tq) {
	+ taskqueue_drain(que->tq, &que->task);
	+ taskqueue_drain(que->tq, &que->tx_task);
	+ taskqueue_free(que->tq);
	+ }
	+ }

	/* Shutdown LAN HMC */
	status = i40e_shutdown_lan_hmc(hw);
	@@ -1138,8 +1136,7 @@
	bcopy(IF_LLADDR(vsi->ifp), tmpaddr,
	I40E_ETH_LENGTH_OF_ADDRESS);
	if (!cmp_etheraddr(hw->mac.addr, tmpaddr) &&
	- (i40e_validate_mac_addr(tmpaddr) == I40E_SUCCESS)) {
	- ixl_del_filter(vsi, hw->mac.addr, IXL_VLAN_ANY);
	+ i40e_validate_mac_addr(tmpaddr)) {
	bcopy(tmpaddr, hw->mac.addr,
	I40E_ETH_LENGTH_OF_ADDRESS);
	ret = i40e_aq_mac_address_write(hw,
	@@ -1149,8 +1146,6 @@
	device_printf(dev, "LLA address"
	"change failed!!\n");
	return;
	- } else {
	- ixl_add_filter(vsi, hw->mac.addr, IXL_VLAN_ANY);
	}
	}

	@@ -1170,7 +1165,6 @@
	#ifdef IXL_FDIR
	filter.enable_fdir = TRUE;
	#endif
	- filter.hash_lut_size = I40E_HASH_LUT_SIZE_512;
	if (i40e_set_filter_control(hw, &filter))
	device_printf(dev, "set_filter_control() failed\n");

	@@ -1455,7 +1449,8 @@
	}

	ifmr->ifm_status \|= IFM_ACTIVE;
	- /* Hardware is always full-duplex */
	+
	+ /* Hardware always does full-duplex */
	ifmr->ifm_active \|= IFM_FDX;

	switch (hw->phy.link_info.phy_type) {
	@@ -1530,6 +1525,7 @@
	case I40E_PHY_TYPE_10GBASE_KR:
	ifmr->ifm_active \|= IFM_10G_KR;
	break;
	+ /* Our single 20G media type */
	case I40E_PHY_TYPE_20GBASE_KR2:
	ifmr->ifm_active \|= IFM_20G_KR2;
	break;
	@@ -1555,14 +1551,11 @@
	return;
	}

	-/*********************************************************************
	- *
	- * Media Ioctl callback
	- *
	- * This routine is called when the user changes speed/duplex using
	- * media/mediopt option with ifconfig.
	- *
	- **********************************************************************/
	+/*
	+ * NOTE: Fortville does not support forcing media speeds. Instead,
	+ * use the set_advertise sysctl to set the speeds Fortville
	+ * will advertise or be allowed to operate at.
	+ */
	static int
	ixl_media_change(struct ifnet * ifp)
	{
	@@ -1574,7 +1567,7 @@
	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
	return (EINVAL);

	- if_printf(ifp, "Media change is currently not supported.\n");
	+ if_printf(ifp, "Media change is not supported.\n");

	return (ENODEV);
	}
	@@ -1988,62 +1981,6 @@
	return (0);
	}

	-static void
	-ixl_init_taskqueues(struct ixl_pf *pf)
	-{
	- struct ixl_vsi *vsi = &pf->vsi;
	- struct ixl_queue *que = vsi->queues;
	- device_t dev = pf->dev;
	-#ifdef RSS
	- int cpu_id;
	- cpuset_t cpu_mask;
	-#endif
	-
	- /* Tasklet for Admin Queue */
	- TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf);
	-#ifdef PCI_IOV
	- /* VFLR Tasklet */
	- TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf);
	-#endif
	-
	- /* Create and start PF taskqueue */
	- pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT,
	- taskqueue_thread_enqueue, &pf->tq);
	- taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq",
	- device_get_nameunit(dev));
	-
	- /* Create queue tasks and start queue taskqueues */
	- for (int i = 0; i < vsi->num_queues; i++, que++) {
	- TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que);
	- TASK_INIT(&que->task, 0, ixl_handle_que, que);
	- que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT,
	- taskqueue_thread_enqueue, &que->tq);
	-#ifdef RSS
	- cpu_id = rss_getcpu(i % rss_getnumbuckets());
	- CPU_SETOF(cpu_id, &cpu_mask);
	- taskqueue_start_threads_cpuset(&que->tq, 1, PI_NET,
	- &cpu_mask, "%s (bucket %d)",
	- device_get_nameunit(dev), cpu_id);
	-#else
	- taskqueue_start_threads(&que->tq, 1, PI_NET,
	- "%s (que %d)", device_get_nameunit(dev), que->me);
	-#endif
	- }
	-}
	-
	-static void
	-ixl_free_taskqueues(struct ixl_pf *pf)
	-{
	- struct ixl_vsi *vsi = &pf->vsi;
	- struct ixl_queue *que = vsi->queues;
	-
	- if (pf->tq)
	- taskqueue_free(pf->tq);
	- for (int i = 0; i < vsi->num_queues; i++, que++) {
	- if (que->tq)
	- taskqueue_free(que->tq);
	- }
	-}

	/*********************************************************************
	*
	@@ -2058,6 +1995,9 @@
	struct ixl_queue *que = vsi->queues;
	struct tx_ring *txr;
	int error, rid, vector = 0;
	+#ifdef RSS
	+ cpuset_t cpu_mask;
	+#endif

	/* Admin Que is vector 0*/
	rid = vector + 1;
	@@ -2079,6 +2019,17 @@
	}
	bus_describe_intr(dev, pf->res, pf->tag, "aq");
	pf->admvec = vector;
	+ /* Tasklet for Admin Queue */
	+ TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf);
	+
	+#ifdef PCI_IOV
	+ TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf);
	+#endif
	+
	+ pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT,
	+ taskqueue_thread_enqueue, &pf->tq);
	+ taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq",
	+ device_get_nameunit(pf->dev));
	++vector;

	/* Now set up the stations */
	@@ -2109,6 +2060,19 @@
	#endif
	bus_bind_intr(dev, que->res, cpu_id);
	que->msix = vector;
	+ TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que);
	+ TASK_INIT(&que->task, 0, ixl_handle_que, que);
	+ que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT,
	+ taskqueue_thread_enqueue, &que->tq);
	+#ifdef RSS
	+ CPU_SETOF(cpu_id, &cpu_mask);
	+ taskqueue_start_threads_cpuset(&que->tq, 1, PI_NET,
	+ &cpu_mask, "%s (bucket %d)",
	+ device_get_nameunit(dev), cpu_id);
	+#else
	+ taskqueue_start_threads(&que->tq, 1, PI_NET,
	+ "%s que", device_get_nameunit(dev));
	+#endif
	}

	return (0);
	@@ -2171,15 +2135,9 @@
	/* Figure out a reasonable auto config value */
	queues = (mp_ncpus > (available - 1)) ? (available - 1) : mp_ncpus;

	- /* Override with hardcoded value if it's less than autoconfig count */
	+ /* Override with hardcoded value if sane */
	if ((ixl_max_queues != 0) && (ixl_max_queues <= queues))
	queues = ixl_max_queues;
	- else if ((ixl_max_queues != 0) && (ixl_max_queues > queues))
	- device_printf(dev, "ixl_max_queues > # of cpus, using "
	- "autoconfig amount...\n");
	- /* Or limit maximum auto-configured queues to 8 */
	- else if ((ixl_max_queues == 0) && (queues > 8))
	- queues = 8;

	#ifdef RSS
	/* If we're doing RSS, clamp at the number of RSS buckets */
	@@ -2279,8 +2237,7 @@

	/* Next configure the queues */
	for (int i = 0; i < vsi->num_queues; i++, vector++) {
	- wr32(hw, I40E_PFINT_DYN_CTLN(i), 0);
	- /* First queue type is RX / type 0 */
	+ wr32(hw, I40E_PFINT_DYN_CTLN(i), i);
	wr32(hw, I40E_PFINT_LNKLSTN(i), i);

	reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK \|
	@@ -2293,8 +2250,11 @@
	reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK \|
	(IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) \|
	(vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) \|
	- (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) \|
	+ ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) \|
	(I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
	+ if (i == (vsi->num_queues - 1))
	+ reg \|= (IXL_QUEUE_EOL
	+ << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
	wr32(hw, I40E_QINT_TQCTL(i), reg);
	}
	}
	@@ -2585,7 +2545,7 @@
	}
	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
	ifp->if_mtu = ETHERMTU;
	- ifp->if_baudrate = IF_Gbps(40);
	+ ifp->if_baudrate = 4000000000; // ??
	ifp->if_init = ixl_init;
	ifp->if_softc = vsi;
	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX \| IFF_MULTICAST;
	@@ -2787,17 +2747,8 @@
	*/
	ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
	ctxt.info.mapping_flags \|= I40E_AQ_VSI_QUE_MAP_CONTIG;
	- /* In contig mode, que_mapping[0] is first queue index used by this VSI */
	- ctxt.info.queue_mapping[0] = 0;
	- /*
	- * This VSI will only use traffic class 0; start traffic class 0's
	- * queue allocation at queue 0, and assign it 64 (2^6) queues (though
	- * the driver may not use all of them).
	- */
	- ctxt.info.tc_mapping[0] = ((0 << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
	- & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) \|
	- ((6 << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
	- & I40E_AQ_VSI_TC_QUE_NUMBER_MASK);
	+ ctxt.info.queue_mapping[0] = 0;
	+ ctxt.info.tc_mapping[0] = 0x0800;

	/* Set VLAN receive stripping mode */
	ctxt.info.valid_sections \|= I40E_AQ_VSI_PROP_VLAN_VALID;
	@@ -2913,6 +2864,7 @@
	device_printf(dev, "Fail in init_rx_ring %d\n", i);
	break;
	}
	+ wr32(vsi->hw, I40E_QRX_TAIL(que->me), 0);
	#ifdef DEV_NETMAP
	/* preserve queue */
	if (vsi->ifp->if_capenable & IFCAP_NETMAP) {
	@@ -4412,7 +4364,6 @@
	IXL_PF_UNLOCK(pf);
	}

	-#ifdef IXL_DEBUG_SYSCTL
	static int
	ixl_debug_info(SYSCTL_HANDLER_ARGS)
	{
	@@ -4477,7 +4428,6 @@
	reg = rd32(hw, I40E_GLPRT_MLFC(hw->port));
	printf("mac local fault = %x\n", reg);
	}
	-#endif

	/**
	* Update VSI-specific ethernet statistics counters.
	@@ -4857,6 +4807,7 @@
	/* Then check for validity based on adapter type */
	switch (hw->device_id) {
	case I40E_DEV_ID_10G_BASE_T:
	+ case I40E_DEV_ID_10G_BASE_T4:
	if (requested_ls & 0x8) {
	device_printf(dev,
	"20Gbs speed not supported on this device.\n");
	@@ -4864,6 +4815,7 @@
	}
	break;
	case I40E_DEV_ID_20G_KR2:
	+ case I40E_DEV_ID_20G_KR2_A:
	if (requested_ls & 0x1) {
	device_printf(dev,
	"100Mbs speed not supported on this device.\n");
	@@ -4902,7 +4854,6 @@
	u16 link;
	u32 offset;

	-
	/* Get the PCI Express Capabilities offset */
	pci_find_cap(dev, PCIY_EXPRESS, &offset);

	@@ -5156,9 +5107,17 @@
	}

	error = sbuf_finish(buf);
	- sbuf_delete(buf);
	+ if (error) {
	+ device_printf(dev, "Error finishing sbuf: %d\n", error);
	+ sbuf_delete(buf);
	+ return error;
	+ }

	- return (error);
	+ error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req);
	+ if (error)
	+ device_printf(dev, "sysctl error: %d\n", error);
	+ sbuf_delete(buf);
	+ return error;
	}

	/*
	@@ -5265,6 +5224,15 @@
	sbuf_delete(nmbuf);

	error = sbuf_finish(buf);
	+ if (error) {
	+ device_printf(dev, "Error finishing sbuf: %d\n", error);
	+ sbuf_delete(buf);
	+ return error;
	+ }
	+
	+ error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req);
	+ if (error)
	+ device_printf(dev, "sysctl error: %d\n", error);
	sbuf_delete(buf);

	return (error);
	@@ -6570,7 +6538,7 @@
	}

	static int
	-ixl_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
	+ixl_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t *params)
	{
	struct ixl_pf *pf;
	struct i40e_hw *hw;
	@@ -6618,7 +6586,7 @@
	}

	static void
	-ixl_iov_uninit(device_t dev)
	+ixl_uninit_iov(device_t dev)
	{
	struct ixl_pf *pf;
	struct i40e_hw *hw;
	@@ -6643,11 +6611,7 @@
	pf->veb_seid = 0;
	}

	-#if __FreeBSD_version > 1100022
	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
	-#else
	- if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
	-#endif
	ixl_disable_intr(vsi);

	vfs = pf->vfs;
	Index: head/sys/dev/ixl/ixl.h
	===================================================================
	--- head/sys/dev/ixl/ixl.h
	+++ head/sys/dev/ixl/ixl.h
	@@ -93,7 +93,6 @@
	#ifdef PCI_IOV
	#include <sys/nv.h>
	#include <sys/iov_schema.h>
	-#include <dev/pci/pci_iov.h>
	#endif

	#include "i40e_type.h"
	@@ -498,6 +497,7 @@
	struct device *dev;
	struct i40e_hw *hw;
	struct ifmedia media;
	+ enum i40e_vsi_type type;
	u64 que_mask;
	int id;
	u16 vsi_num;
	@@ -512,9 +512,11 @@
	u16 uplink_seid;
	u16 downlink_seid;
	u16 max_frame_size;
	+ u16 rss_table_size;
	+ u16 rss_size;

	/* MAC/VLAN Filter list */
	- struct ixl_ftl_head ftl;
	+ struct ixl_ftl_head ftl;
	u16 num_macs;

	struct i40e_aqc_vsi_properties_data info;
	Index: head/sys/dev/ixl/ixl_txrx.c
	===================================================================
	--- head/sys/dev/ixl/ixl_txrx.c
	+++ head/sys/dev/ixl/ixl_txrx.c
	@@ -286,7 +286,7 @@
	if (error == EFBIG) {
	struct mbuf *m;

	- m = m_defrag(*m_headp, M_NOWAIT);
	+ m = m_collapse(*m_headp, M_NOWAIT, maxsegs);
	if (m == NULL) {
	que->mbuf_defrag_failed++;
	m_freem(*m_headp);
	@@ -390,6 +390,7 @@
	++txr->total_packets;
	wr32(hw, txr->tail, i);

	+ ixl_flush(hw);
	/* Mark outstanding work */
	if (que->busy == 0)
	que->busy = 1;
	Index: head/sys/dev/ixl/ixlv_vc_mgr.h
	===================================================================
	--- head/sys/dev/ixl/ixlv_vc_mgr.h
	+++ head/sys/dev/ixl/ixlv_vc_mgr.h
	@@ -1,6 +1,6 @@
	/******************************************************************************

	- Copyright (c) 2013-2014, Intel Corporation
	+ Copyright (c) 2013-2015, Intel Corporation
	All rights reserved.

	Redistribution and use in source and binary forms, with or without

File Metadata

Mime Type: text/plain
Expires: Sat, May 3, 6:42 AM (13 h, 33 m)
Storage Engine: blob
Storage Format: Raw Data
Storage Handle: 17926589
Default Alt Text: D6211.diff (191 KB)

D6211.diffNo OneTemporaryActions

D6211.diffView Options

File Metadata

Event Timeline

D6211.diff
No OneTemporary
Actions

D6211.diff
View Options