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diff --git a/sys/riscv/include/md_var.h b/sys/riscv/include/md_var.h
--- a/sys/riscv/include/md_var.h
+++ b/sys/riscv/include/md_var.h
@@ -46,6 +46,9 @@
extern bool has_sscofpmf;
extern bool has_svpbmt;
+/* CPU errata presence */
+extern bool has_errata_thead_pbmt;
+
struct dumperinfo;
struct minidumpstate;
diff --git a/sys/riscv/include/pte.h b/sys/riscv/include/pte.h
--- a/sys/riscv/include/pte.h
+++ b/sys/riscv/include/pte.h
@@ -102,6 +102,25 @@
#define PTE_MA_NC (1ul << PTE_MA_SHIFT)
#define PTE_MA_IO (2ul << PTE_MA_SHIFT)
+/*
+ * T-HEAD Custom Memory Attribute (MA) bits [63:59].
+ *
+ * +------+-------+----------------------------------------------------------------+
+ * | Mode | Value | Requested Memory Attributes |
+ * +------+-------+----------------------------------------------------------------+
+ * | NC | 00000 | Non-cacheable, non-bufferable, non-shareable, non-trustable, |
+ * | | | weakly-ordered. |
+ * | PMA | 01110 | Non-cacheable, idempotent, weakly-ordered (RVWMO), main memory |
+ * | IO | 10000 | Strongly-ordered, non-cacheable, non-bufferable, non-shareable |
+ * +------+-------+----------------------------------------------------------------+
+ */
+#define PTE_THEAD_MA_SHIFT 59
+#define PTE_THEAD_MA_MASK (0x1ful << PTE_MA_SHIFT)
+#define PTE_THEAD_MA_TO_MODE(pte) ((pte & PTE_MA_MASK) >> PTE_MA_SHIFT)
+#define PTE_THEAD_MA_NC (0x0ul << PTE_MA_SHIFT)
+#define PTE_THEAD_MA_NONE (0xeul << PTE_MA_SHIFT)
+#define PTE_THEAD_MA_IO (0x10ul << PTE_MA_SHIFT)
+
/* Bits 63 - 54 are reserved for future use. */
#define PTE_HI_MASK 0xFFC0000000000000ULL
diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
--- a/sys/riscv/riscv/identcpu.c
+++ b/sys/riscv/riscv/identcpu.c
@@ -76,6 +76,9 @@
bool __read_frequently has_sscofpmf;
bool __read_frequently has_svpbmt;
+/* CPU errata */
+bool has_errata_thead_pbmt;
+
struct cpu_desc {
const char *cpu_mvendor_name;
const char *cpu_march_name;
@@ -459,6 +462,22 @@
}
}
+static void
+update_cpu_errata_thead(u_int cpu, struct cpu_desc *desc)
+{
+ has_errata_thead_pbmt = true;
+}
+
+static void
+update_cpu_errata(u_int cpu, struct cpu_desc *desc)
+{
+ switch (mvendorid) {
+ case MVENDORID_THEAD:
+ update_cpu_errata_thead(cpu, desc);
+ break;
+ }
+}
+
void
identify_cpu(u_int cpu)
{
@@ -467,6 +486,7 @@
identify_cpu_ids(desc);
identify_cpu_features(cpu, desc);
+ update_cpu_errata(cpu, desc);
update_global_capabilities(cpu, desc);
}
diff --git a/sys/riscv/riscv/pmap.c b/sys/riscv/riscv/pmap.c
--- a/sys/riscv/riscv/pmap.c
+++ b/sys/riscv/riscv/pmap.c
@@ -536,6 +536,7 @@
* lacking Svpbmt extension.
*/
static __read_frequently pt_entry_t memattr_bits[VM_MEMATTR_TOTAL];
+static __read_frequently pt_entry_t memattr_mask;
static __inline pt_entry_t
pmap_memattr_bits(vm_memattr_t mode)
@@ -858,6 +859,12 @@
memattr_bits[VM_MEMATTR_PMA] = PTE_MA_NONE;
memattr_bits[VM_MEMATTR_UNCACHEABLE] = PTE_MA_NC;
memattr_bits[VM_MEMATTR_DEVICE] = PTE_MA_IO;
+ memattr_mask = PTE_THEAD_MA_MASK;
+ } else if (has_errata_thead_pbmt) {
+ memattr_bits[VM_MEMATTR_PMA] = PTE_THEAD_MA_NONE;
+ memattr_bits[VM_MEMATTR_UNCACHEABLE] = PTE_THEAD_MA_NC;
+ memattr_bits[VM_MEMATTR_DEVICE] = PTE_THEAD_MA_IO;
+ memattr_mask = PTE_MA_MASK;
}
/* Create a new set of pagetables to run the kernel in. */
@@ -4761,7 +4768,7 @@
return (EINVAL);
bits = pmap_memattr_bits(mode);
- mask = PTE_MA_MASK;
+ mask = memattr_mask;
/* First loop: perform PTE validation and demotions as necessary. */
for (tmpva = base; tmpva < base + size; ) {
@@ -5172,11 +5179,16 @@
vm_offset_t eva)
{
char *mode;
+ int i;
if (eva <= range->sva)
return;
- switch (PTE_MA_TO_MODE(range->attrs)) {
+ for (i = 0; i < nitems(memattr_bits); i++)
+ if ((range->attrs & memattr_mask) == memattr_bits[i])
+ break;
+
+ switch (i) {
case VM_MEMATTR_PMA:
mode = "PMA";
break;
@@ -5239,16 +5251,16 @@
attrs = l1e & PTE_G;
if ((l1e & PTE_RWX) != 0) {
attrs |= l1e & (PTE_RWX | PTE_U);
- attrs |= l1e & PTE_MA_MASK;
+ attrs |= l1e & memattr_mask;
} else if (l2e != 0)
attrs |= l2e & PTE_G;
if ((l2e & PTE_RWX) != 0) {
attrs |= l2e & (PTE_RWX | PTE_U);
- attrs |= l2e & PTE_MA_MASK;
+ attrs |= l2e & memattr_mask;
} else if (l3e != 0) {
attrs |= l3e & (PTE_RWX | PTE_U | PTE_G);
- attrs |= l3e & PTE_MA_MASK;
+ attrs |= l3e & memattr_mask;
}
if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {

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