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diff --git a/sys/arm64/arm64/busdma_bounce.c b/sys/arm64/arm64/busdma_bounce.c
--- a/sys/arm64/arm64/busdma_bounce.c
+++ b/sys/arm64/arm64/busdma_bounce.c
@@ -162,32 +162,6 @@
return (error);
}
-/*
- * Return true if the DMA should bounce because the start or end does not fall
- * on a cacheline boundary (which would require a partial cacheline flush).
- * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by
- * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a
- * strict rule that such memory cannot be accessed by the CPU while DMA is in
- * progress (or by multiple DMA engines at once), so that it's always safe to do
- * full cacheline flushes even if that affects memory outside the range of a
- * given DMA operation that doesn't involve the full allocated buffer. If we're
- * mapping an mbuf, that follows the same rules as a buffer we allocated.
- */
-static bool
-cacheline_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
- bus_size_t size)
-{
-
-#define DMAMAP_CACHELINE_FLAGS \
- (DMAMAP_FROM_DMAMEM | DMAMAP_COHERENT | DMAMAP_MBUF)
- if ((dmat->common.flags & BUS_DMA_COHERENT) != 0)
- return (false);
- if (map != NULL && (map->flags & DMAMAP_CACHELINE_FLAGS) != 0)
- return (false);
- return (((paddr | size) & (dcache_line_size - 1)) != 0);
-#undef DMAMAP_CACHELINE_FLAGS
-}
-
/*
* Return true if the given address does not fall on the alignment boundary.
*/
@@ -712,6 +686,33 @@
};
/* busdma support for non-coherent devices */
+
+/*
+ * Return true if the DMA should bounce because the start or end does not fall
+ * on a cacheline boundary (which would require a partial cacheline flush).
+ * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by
+ * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a
+ * strict rule that such memory cannot be accessed by the CPU while DMA is in
+ * progress (or by multiple DMA engines at once), so that it's always safe to do
+ * full cacheline flushes even if that affects memory outside the range of a
+ * given DMA operation that doesn't involve the full allocated buffer. If we're
+ * mapping an mbuf, that follows the same rules as a buffer we allocated.
+ */
+static bool
+cacheline_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
+ bus_size_t size)
+{
+
+#define DMAMAP_CACHELINE_FLAGS \
+ (DMAMAP_FROM_DMAMEM | DMAMAP_COHERENT | DMAMAP_MBUF)
+ if ((dmat->common.flags & BUS_DMA_COHERENT) != 0)
+ return (false);
+ if (map != NULL && (map->flags & DMAMAP_CACHELINE_FLAGS) != 0)
+ return (false);
+ return (((paddr | size) & (dcache_line_size - 1)) != 0);
+#undef DMAMAP_CACHELINE_FLAGS
+}
+
#define BUS_DMA_NON_COHERENT_IMPL
#include "busdma_bounce.h"

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