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D29764.diff
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diff --git a/sys/riscv/riscv/trap.c b/sys/riscv/riscv/trap.c
--- a/sys/riscv/riscv/trap.c
+++ b/sys/riscv/riscv/trap.c
@@ -274,6 +274,9 @@
KASSERT((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) ==
SSTATUS_SPP, ("Came from S mode with interrupts enabled"));
+ KASSERT((csr_read(sstatus) & (SSTATUS_SUM)) == 0,
+ ("Came from S mode with SUM enabled"));
+
exception = frame->tf_scause & SCAUSE_CODE;
if ((frame->tf_scause & SCAUSE_INTR) != 0) {
/* Interrupt */
@@ -342,6 +345,9 @@
KASSERT((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) == 0,
("Came from U mode with interrupts enabled"));
+ KASSERT((csr_read(sstatus) & (SSTATUS_SUM)) == 0,
+ ("Came from U mode with SUM enabled"));
+
exception = frame->tf_scause & SCAUSE_CODE;
if ((frame->tf_scause & SCAUSE_INTR) != 0) {
/* Interrupt */
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D29764: riscv: Assert that SUM is not set in SSTATUS for exceptions.
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