D33981.id103086.diff
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D33981.id103086.diff
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	diff --git a/sys/dev/sdhci/sdhci_fsl_fdt.c b/sys/dev/sdhci/sdhci_fsl_fdt.c
	--- a/sys/dev/sdhci/sdhci_fsl_fdt.c
	+++ b/sys/dev/sdhci/sdhci_fsl_fdt.c
	@@ -885,16 +885,6 @@
	sc->slot.max_clk = sc->maxclk_hz;
	sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);

	- /*
	- * Pulse width detection is not reliable on some boards. Perform
	- * workaround by clearing register's bit according to errata.
	- */
	- if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) {
	- val = RD4(sc, SDHCI_FSL_DLLCFG1);
	- val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH;
	- WR4(sc, SDHCI_FSL_DLLCFG1, val);
	- }
	-
	/*
	* Set the buffer watermark level to 128 words (512 bytes) for both
	* read and write. The hardware has a restriction that when the read or
	@@ -1028,6 +1018,16 @@
	WR4(sc, SDHCI_FSL_TBCTL, val);
	}

	+ /*
	+ * Pulse width detection is not reliable on some boards. Perform
	+ * workaround by clearing register's bit according to errata.
	+ */
	+ if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) {
	+ val = RD4(sc, SDHCI_FSL_DLLCFG1);
	+ val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH;
	+ WR4(sc, SDHCI_FSL_DLLCFG1, val);
	+ }
	+
	sc->flags &= ~SDHCI_FSL_HS400_DONE;
	}