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diff --git a/sys/dev/cadence/if_cgem.c b/sys/dev/cadence/if_cgem.c
--- a/sys/dev/cadence/if_cgem.c
+++ b/sys/dev/cadence/if_cgem.c
@@ -77,9 +77,7 @@
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
-#ifdef EXT_RESOURCES
#include <dev/extres/clk/clk.h>
-#endif
#if BUS_SPACE_MAXADDR > BUS_SPACE_MAXADDR_32BIT
#define CGEM64
@@ -130,11 +128,7 @@
struct callout tick_ch;
uint32_t net_ctl_shadow;
uint32_t net_cfg_shadow;
-#ifdef EXT_RESOURCES
clk_t ref_clk;
-#else
- int ref_clk_num;
-#endif
int neednullqs;
bus_dma_tag_t desc_dma_tag;
@@ -1497,7 +1491,6 @@
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
-#ifdef EXT_RESOURCES
if (sc->ref_clk != NULL) {
CGEM_UNLOCK(sc);
if (clk_set_freq(sc->ref_clk, ref_clk_freq, 0))
@@ -1505,13 +1498,6 @@
ref_clk_freq);
CGEM_LOCK(sc);
}
-#else
- /* Set the reference clock if necessary. */
- if (cgem_set_ref_clk(sc->ref_clk_num, ref_clk_freq))
- device_printf(sc->dev,
- "cgem_mediachange: could not set ref clk%d to %d.\n",
- sc->ref_clk_num, ref_clk_freq);
-#endif
sc->mii_media_active = mii->mii_media_active;
}
@@ -1741,10 +1727,6 @@
int rid, err;
u_char eaddr[ETHER_ADDR_LEN];
int hwtype;
-#ifndef EXT_RESOURCES
- phandle_t node;
- pcell_t cell;
-#endif
sc->dev = dev;
CGEM_LOCK_INIT(sc);
@@ -1756,7 +1738,6 @@
if (hwtype == HWTYPE_ZYNQ)
sc->rxhangwar = 1;
-#ifdef EXT_RESOURCES
if (hwtype == HWTYPE_ZYNQ || hwtype == HWTYPE_ZYNQMP) {
if (clk_get_by_ofw_name(dev, 0, "tx_clk", &sc->ref_clk) != 0)
device_printf(dev,
@@ -1770,13 +1751,6 @@
else if (clk_enable(sc->ref_clk) != 0)
device_printf(dev, "could not enable clock.\n");
}
-#else
- /* Get reference clock number and base divider from fdt. */
- node = ofw_bus_get_node(dev);
- sc->ref_clk_num = 0;
- if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell)) > 0)
- sc->ref_clk_num = fdt32_to_cpu(cell);
-#endif
/* Get memory resource. */
rid = 0;
@@ -1939,12 +1913,10 @@
sc->mbuf_dma_tag = NULL;
}
-#ifdef EXT_RESOURCES
if (sc->ref_clk != NULL) {
clk_release(sc->ref_clk);
sc->ref_clk = NULL;
}
-#endif
bus_generic_detach(dev);

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