D40890.diff
No OneTemporary
Actions

Size

6 KB

Referenced Files

None

Subscribers

None

D40890.diff
View Options

	diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
	--- a/sys/arm64/arm64/identcpu.c
	+++ b/sys/arm64/arm64/identcpu.c
	@@ -935,6 +935,17 @@


	/* ID_AA64MMFR0_EL1 */
	+static const struct mrs_field_value id_aa64mmfr0_ecv[] = {
	+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ECV, NONE, IMPL),
	+ MRS_FIELD_VALUE(ID_AA64MMFR0_ECV_CNTHCTL, "ECV+CNTHCTL"),
	+ MRS_FIELD_VALUE_END,
	+};
	+
	+static const struct mrs_field_value id_aa64mmfr0_fgt[] = {
	+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, FGT, NONE, IMPL),
	+ MRS_FIELD_VALUE_END,
	+};
	+
	static const struct mrs_field_value id_aa64mmfr0_exs[] = {
	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
	MRS_FIELD_VALUE_END,
	@@ -944,6 +955,7 @@
	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""),
	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"),
	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"),
	+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_LPA2, "S2 TGran4+LPA2"),
	MRS_FIELD_VALUE_END,
	};

	@@ -958,11 +970,13 @@
	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""),
	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"),
	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"),
	+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_LPA2, "S2 TGran16+LPA2"),
	MRS_FIELD_VALUE_END,
	};

	static const struct mrs_field_value id_aa64mmfr0_tgran4[] = {
	- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL),
	+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
	+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_LPA2, "TGran4+LPA2"),
	MRS_FIELD_VALUE_END,
	};

	@@ -973,6 +987,7 @@

	static const struct mrs_field_value id_aa64mmfr0_tgran16[] = {
	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL),
	+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_LPA2, "TGran16+LPA2"),
	MRS_FIELD_VALUE_END,
	};

	@@ -1009,6 +1024,8 @@
	};

	static const struct mrs_field id_aa64mmfr0_fields[] = {
	+ MRS_FIELD(ID_AA64MMFR0, ECV, false, MRS_EXACT, id_aa64mmfr0_ecv),
	+ MRS_FIELD(ID_AA64MMFR0, FGT, false, MRS_EXACT, id_aa64mmfr0_fgt),
	MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs),
	MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT,
	id_aa64mmfr0_tgran4_2),
	diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
	--- a/sys/arm64/include/armreg.h
	+++ b/sys/arm64/include/armreg.h
	@@ -804,11 +804,11 @@

	/* ID_AA64MMFR0_EL1 */
	#define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1)
	-#define ID_AA64MMFR0_EL1_op0 0x3
	-#define ID_AA64MMFR0_EL1_op1 0x0
	-#define ID_AA64MMFR0_EL1_CRn 0x0
	-#define ID_AA64MMFR0_EL1_CRm 0x7
	-#define ID_AA64MMFR0_EL1_op2 0x0
	+#define ID_AA64MMFR0_EL1_op0 3
	+#define ID_AA64MMFR0_EL1_op1 0
	+#define ID_AA64MMFR0_EL1_CRn 0
	+#define ID_AA64MMFR0_EL1_CRm 7
	+#define ID_AA64MMFR0_EL1_op2 0
	#define ID_AA64MMFR0_PARange_SHIFT 0
	#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
	#define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK)
	@@ -844,6 +844,7 @@
	#define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK)
	#define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
	#define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
	+#define ID_AA64MMFR0_TGran16_LPA2 (UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT)
	#define ID_AA64MMFR0_TGran64_SHIFT 24
	#define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
	#define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK)
	@@ -853,6 +854,7 @@
	#define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
	#define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK)
	#define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
	+#define ID_AA64MMFR0_TGran4_LPA2 (UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT)
	#define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
	#define ID_AA64MMFR0_TGran16_2_SHIFT 32
	#define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
	@@ -860,6 +862,7 @@
	#define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
	#define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
	#define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
	+#define ID_AA64MMFR0_TGran16_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT)
	#define ID_AA64MMFR0_TGran64_2_SHIFT 36
	#define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
	#define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK)
	@@ -872,19 +875,31 @@
	#define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
	#define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
	#define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
	+#define ID_AA64MMFR0_TGran4_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT)
	#define ID_AA64MMFR0_ExS_SHIFT 44
	#define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
	#define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK)
	#define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
	#define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
	+#define ID_AA64MMFR0_FGT_SHIFT 56
	+#define ID_AA64MMFR0_FGT_MASK (UL(0xf) << ID_AA64MMFR0_FGT_SHIFT)
	+#define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK)
	+#define ID_AA64MMFR0_FGT_NONE (UL(0x0) << ID_AA64MMFR0_FGT_SHIFT)
	+#define ID_AA64MMFR0_FGT_IMPL (UL(0x1) << ID_AA64MMFR0_FGT_SHIFT)
	+#define ID_AA64MMFR0_ECV_SHIFT 60
	+#define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT)
	+#define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK)
	+#define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT)
	+#define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT)
	+#define ID_AA64MMFR0_ECV_CNTHCTL (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT)

	/* ID_AA64MMFR1_EL1 */
	#define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1)
	-#define ID_AA64MMFR1_EL1_op0 0x3
	-#define ID_AA64MMFR1_EL1_op1 0x0
	-#define ID_AA64MMFR1_EL1_CRn 0x0
	-#define ID_AA64MMFR1_EL1_CRm 0x7
	-#define ID_AA64MMFR1_EL1_op2 0x1
	+#define ID_AA64MMFR1_EL1_op0 3
	+#define ID_AA64MMFR1_EL1_op1 0
	+#define ID_AA64MMFR1_EL1_CRn 0
	+#define ID_AA64MMFR1_EL1_CRm 7
	+#define ID_AA64MMFR1_EL1_op2 1
	#define ID_AA64MMFR1_HAFDBS_SHIFT 0
	#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
	#define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)

File Metadata

Mime Type: text/plain
Expires: Mon, Jan 13, 11:55 PM (20 h, 56 m)
Storage Engine: blob
Storage Format: Raw Data
Storage Handle: 15788887
Default Alt Text: D40890.diff (6 KB)

D40890.diffNo OneTemporaryActions

D40890.diffView Options

File Metadata

Event Timeline

D40890.diff
No OneTemporary
Actions

D40890.diff
View Options