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diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -279,7 +279,7 @@
cr4 = rcr4();
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
cr4 |= CR4_FXSR | CR4_XMM;
- cpu_fxsr = hw_instruction_sse = 1;
+ hw_instruction_sse = 1;
}
if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
cr4 |= CR4_FSGSBASE;
diff --git a/sys/i386/i386/npx.c b/sys/i386/i386/npx.c
--- a/sys/i386/i386/npx.c
+++ b/sys/i386/i386/npx.c
@@ -175,6 +175,7 @@
&lazy_fpu_switch, 0,
"Lazily load FPU context after context switch");
+u_int cpu_fxsr; /* SSE enabled */
int use_xsave;
uint64_t xsave_mask;
static uma_zone_t fpu_save_area_zone;
diff --git a/sys/i386/include/md_var.h b/sys/i386/include/md_var.h
--- a/sys/i386/include/md_var.h
+++ b/sys/i386/include/md_var.h
@@ -36,6 +36,7 @@
#include <x86/x86_var.h>
+extern u_int cpu_fxsr;
extern u_int cyrix_did;
#if defined(I586_CPU) && !defined(NO_F00F_HACK)
extern int has_f00f_bug;
diff --git a/sys/x86/include/x86_var.h b/sys/x86/include/x86_var.h
--- a/sys/x86/include/x86_var.h
+++ b/sys/x86/include/x86_var.h
@@ -53,7 +53,6 @@
extern u_int cpu_stdext_feature2;
extern u_int cpu_stdext_feature3;
extern uint64_t cpu_ia32_arch_caps;
-extern u_int cpu_fxsr;
extern u_int cpu_high;
extern u_int cpu_id;
extern u_int cpu_max_ext_state_size;
diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c
--- a/sys/x86/x86/identcpu.c
+++ b/sys/x86/x86/identcpu.c
@@ -106,7 +106,6 @@
u_int cpu_procinfo2; /* Multicore info */
char cpu_vendor[20]; /* CPU Origin code */
u_int cpu_vendor_id; /* CPU vendor ID */
-u_int cpu_fxsr; /* SSE enabled */
u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
u_int cpu_clflush_line_size = 32;
u_int cpu_stdext_feature; /* %ebx */

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