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D44522.diff
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diff --git a/sys/amd64/amd64/fpu.c b/sys/amd64/amd64/fpu.c
--- a/sys/amd64/amd64/fpu.c
+++ b/sys/amd64/amd64/fpu.c
@@ -850,7 +850,10 @@
struct pcb *pcb;
uint64_t *xstate_bv, bit;
char *sa;
+ struct savefpu *s;
+ uint32_t mxcsr, mxcsr_mask;
int max_ext_n, i, owned;
+ bool do_mxcsr;
pcb = td->td_pcb;
critical_enter();
@@ -881,10 +884,28 @@
bit = 1ULL << i;
if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
continue;
+ do_mxcsr = false;
+ if (i == 0 && (*xstate_bv & (XFEATURE_ENABLED_SSE |
+ XFEATURE_ENABLED_AVX)) != 0) {
+ /*
+ * x87 area was not saved by XSAVEOPT,
+ * but one of XMM or AVX was. Then we need
+ * to preserve MXCSR from being overwritten
+ * with the default value.
+ */
+ s = (struct savefpu *)sa;
+ mxcsr = s->sv_env.en_mxcsr;
+ mxcsr_mask = s->sv_env.en_mxcsr_mask;
+ do_mxcsr = true;
+ }
bcopy((char *)fpu_initialstate +
xsave_area_desc[i].offset,
sa + xsave_area_desc[i].offset,
xsave_area_desc[i].size);
+ if (do_mxcsr) {
+ s->sv_env.en_mxcsr = mxcsr;
+ s->sv_env.en_mxcsr_mask = mxcsr_mask;
+ }
*xstate_bv |= bit;
}
}
diff --git a/sys/i386/i386/npx.c b/sys/i386/i386/npx.c
--- a/sys/i386/i386/npx.c
+++ b/sys/i386/i386/npx.c
@@ -975,8 +975,11 @@
struct pcb *pcb;
uint64_t *xstate_bv, bit;
char *sa;
+ union savefpu *s;
+ uint32_t mxcsr, mxcsr_mask;
int max_ext_n, i;
int owned;
+ bool do_mxcsr;
if (!hw_float)
return (_MC_FPOWNED_NONE);
@@ -1019,10 +1022,28 @@
bit = 1ULL << i;
if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
continue;
+ do_mxcsr = false;
+ if (i == 0 && (*xstate_bv & (XFEATURE_ENABLED_SSE |
+ XFEATURE_ENABLED_AVX)) != 0) {
+ /*
+ * x87 area was not saved by XSAVEOPT,
+ * but one of XMM or AVX was. Then we need
+ * to preserve MXCSR from being overwritten
+ * with the default value.
+ */
+ s = (union savefpu *)sa;
+ mxcsr = s->sv_xmm.sv_env.en_mxcsr;
+ mxcsr_mask = s->sv_xmm.sv_env.en_mxcsr_mask;
+ do_mxcsr = true;
+ }
bcopy((char *)npx_initialstate +
xsave_area_desc[i].offset,
sa + xsave_area_desc[i].offset,
xsave_area_desc[i].size);
+ if (do_mxcsr) {
+ s->sv_xmm.sv_env.en_mxcsr = mxcsr;
+ s->sv_xmm.sv_env.en_mxcsr_mask = mxcsr_mask;
+ }
*xstate_bv |= bit;
}
}
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D44522: amd64: handle MXCSR from XSAVEOPT when x87 state was optimized
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