Add StarFive JH7110's STG clocks

[jsihv_gmx.com]

Summary

This is identical to AON clocks. The only difference is "BUS_PASS_ORDER_LAST" which was needed for some reason. This has clocks needed by PCIE controller driver.

[mhorne]

Thanks for handling this, I was beginning to experiment with the USB controller and need the STG clocks for it.

Please also enable the driver in sys/riscv/starfive/files.starfive.

sys/dev/clk/starfive/jh7110_clk_stg.c

5–6

I think there is nothing remaining in this file to require their copyrights.

206

The requirement you mention is because the SYS clock driver must attach first. My suggestion is to organize it in the following way:

PLL: BUS_PASS_BUS + BUS_PASS_ORDER_EARLY
SYS: BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE
AON/STG: BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE + 1

[mhorne]

BTW, I needed to add the following SYS clock in order for the STG driver to attach successfully:

diff --git a/sys/dev/clk/starfive/jh7110_clk_sys.c b/sys/dev/clk/starfive/jh7110_clk_sys.c
index e7b8aa87c48e..d4c9a33e8628 100644
--- a/sys/dev/clk/starfive/jh7110_clk_sys.c
+++ b/sys/dev/clk/starfive/jh7110_clk_sys.c
@@ -65,6 +65,7 @@ static const char *u1_dw_uart_clk_apb_p[] = { "apb0" };
 static const char *u1_dw_uart_clk_core_p[] = { "osc" };
 static const char *u1_dw_sdio_clk_ahb_p[] = { "ahb0" };
 static const char *u1_dw_sdio_clk_sdcard_p[] = { "axi_cfg0" };
+static const char *usb_125m_p[] = { "pll0_out" };
 static const char *u2_dw_uart_clk_apb_p[] = { "apb0" };
 static const char *u2_dw_uart_clk_core_p[] = { "osc" };
 static const char *u3_dw_uart_clk_apb_p[] = { "apb0" };
@@ -127,6 +128,7 @@ static const struct jh7110_clk_def sys_clks[] = {
 	    u0_dw_sdio_clk_sdcard_p, 15),
 	JH7110_GATEDIV(JH7110_SYSCLK_SDIO1_SDCARD, "u1_dw_sdio_clk_sdcard",
 	    u1_dw_sdio_clk_sdcard_p, 15),
+	JH7110_DIV(JH7110_SYSCLK_USB_125M, "usb_125m", usb_125m_p, 15),
 
 	JH7110_DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", gmac_src_p, 7),
 	JH7110_GATEDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk",

[jsihv_gmx.com]

Redundant credits removed, BUS_PASS_ORDER modified

sys/dev/clk/starfive/jh7110_clk_stg.c

206

While theoretically sound, your proposed solution actually causes a panic at least in my system. If SYS file has BUS_PASS_ORDER_MIDDLE it's not found before PLL for some reason.

I also tried your solution with PLL changed to BUS_PASS_ORDER_FIRST but it doesn't work either.

A solution which I find working in the practice is:
PLL: BUS_PASS_BUS + BUS_PASS_ORDER_EARLY
SYS: BUS_PASS_BUS + BUS_PASS_ORDER_LATE
AON/STG: BUS_PASS_BUS + BUS_PASS_ORDER_LATE + 1

(It actually still complains about PLL not finding syscon ("jh7110_clk_pll0: Failed to find syscon node") but finds it eventually)

[jsihv_gmx.com]

sys/dev/clk/starfive/jh7110_clk_stg.c

206

Correction: PLL file is not found _before_ SYS file if SYS has BUS_PASS_ORDER_MIDDLE (despite of PLL having BUS_PASS_ORDER_EARLY/FIRST)

[jsihv_gmx.com]

Now adding this file to files.starfive

[mhorne]

sys/dev/clk/starfive/jh7110_clk_stg.c

39

Why RF_SHAREABLE?

69–95

In practical terms, it does not matter, but I would sort these entries based on their clock IDs (ascending order) in dt-bindings/clock/starfive,jh7110-crg.h.

206

Ack, I think it is due to simple_mfd subclass, but I would have to investigate further. What you have here is fine for this change.

[jsihv_gmx.com]

RF_SHAREABLE removed, clocks rearranged to header file's order

[jsihv_gmx.com]

sys/dev/clk/starfive/jh7110_clk_stg.c

39

For no reason. Removed.

[mhorne]

Thanks much. I will pull this change today.

Just so it's known: I intend to look at the other larger reviews soon. The ethernet driver in particular needs some action on my part to move forward.