This driver requires jh7110_gpio.c and jh7110_clk_stg.c
JH7110 has two PCIE controller devices. First one is used by board's integrated USB which has no driver. Switching PHY to USB mode is not currently implemented. This functionality could be added in a form of a separate PCIE PHY driver if needed. PHY is on by default and there's no need to switch it on.
Pre/post_ithread and post_filter methods are not used for interrupt masking since they are meant for level-triggered interrupts whereas JH7110's MSI interrupts are edge triggered (and INTx interrupts do not use this irqsrc scheme at all). Pre_ithread method is nevertheless used for MSI bottom acking.
The driver has been tested with Kingston SNV2S NVME SSD
The functionality of INTx and MSI interrupts (as opposed to default MSIx) has been tested by forcing NVME to use them
There is a some kind of problem with memory allocation which happens in function pci_pci.c:pcib_probe_windows(). It seems the function and its PCI_PPBMEMBASE() macro are not capable of dealing with 64-bit addresses in cases when both 32-bit parts are used to form the address. This problem concerns the address 0x980000000 [0x9 0x80000000] which is used by the second PCIE device. The rejection of a formed faulty address eventually happens in subr_rman.c:rman_reserve_resource_bound(). Other pcie-drivers which fetch ranges (tegra_pcie.c, rk_pcie.c) seem to only use shorter one part addresses on their device trees. This problem leads to one failed memory allocation during the boot but seems not to stop the device from functioning.